參數(shù)資料
型號(hào): XRT83VSH28
廠商: Exar Corporation
英文描述: 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 8路E1短途線路接口單元
文件頁(yè)數(shù): 61/74頁(yè)
文件大小: 574K
代理商: XRT83VSH28
PRELIMINARY
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH28
58
REV. P1.0.0
N
OTE
:
Any change in status will generate an interrupt (if enabled in channel register 0x04h and GIE is set to "1" in the
global register 0x80h). The status registers are reset upon read (RUR).
D1
RLOSIS
Receiver Loss of Signal Status
0 = No change
1 = Change in status occurred
RUR
0
D0
QRPDIS
Quasi Random Pattern Detection Status
0 = No change
1 = Change in status occurred
RUR
0
T
ABLE
26: M
ICROPROCESSOR
R
EGISTER
0
X
08
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
08
H
-0
X
78
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D6
D5
D4
D3
D2
D1
D0
1SEG6
1SEG5
1SEG4
1SEG3
1SEG2
1SEG1
1SEG0
Arbitrary Pulse Generation
The transmit output pulse is divided into 8 individual segments.
This register is used to program the first segment which corre-
sponds to the overshoot of the pulse amplitude. There are four
segments for the top portion of the pulse and four segments for the
bottom portion of the pulse. Segment number 5 corresponds to
the undershoot of the pulse. The MSB of each segment is the sign
bit.
Bit 6 = 0 = Negative Direction
Bit 6 = 1 = Positive Direction
R/W
0
0
0
0
0
0
0
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
0
X
09
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
09
H
-0
X
79
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D[6:0]
2SEG[6:0]
Segment Number Two, Same Description as Register 0x08h
R/W
T
ABLE
25: M
ICROPROCESSOR
R
EGISTER
0
X
06
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
06
H
-0
X
76
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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