參數(shù)資料
型號： XRT83VSH28
廠商： Exar Corporation
英文描述： 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 8路E1短途線路接口單元
文件頁數(shù)： 6/74頁
文件大小： 574K
代理商： XRT83VSH28
XRT83VSH28
PRELIMINARY
II
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.0
3.5.3 ARBITRARY PULSE GENERATOR FOR E1............................................................................................................. 30
F
IGURE
18. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
.................................................................................................................. 30
3.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30
3.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 31
F
IGURE
19. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
................................................................................... 31
4.0 E1 APPLICATIONS ..............................................................................................................................32
4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32
4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32
F
IGURE
20. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
L
OCAL
A
NALOG
L
OOPBACK
......................................................................................... 32
4.1.2 REMOTE LOOPBACK................................................................................................................................................ 32
F
IGURE
21. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
R
EMOTE
L
OOPBACK
.................................................................................................... 32
4.1.3 DIGITAL LOOPBACK................................................................................................................................................. 33
F
IGURE
22. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
IGITAL
L
OOPBACK
..................................................................................................... 33
4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33
F
IGURE
23. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
UAL
L
OOPBACK
........................................................................................................ 33
4.2 LINE CARD REDUNDANCY ........................................................................................................................... 34
4.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS.................................................................................................... 34
4.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY.................................................................................. 34
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
......................................... 34
4.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 35
F
IGURE
25. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
........................................... 35
4.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36
4.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
F
IGURE
26. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
N+1 R
EDUNDANCY
...................................................... 36
4.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY................................................................................................... 37
F
IGURE
27. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
N+1 R
EDUNDANCY
........................................................ 37
4.3 POWER FAILURE PROTECTION .................................................................................................................. 38
4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
4.5 NON-INTRUSIVE MONITORING .................................................................................................................... 38
F
IGURE
28. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
............................................................... 38
5.0 MICROPROCESSOR INTERFACE ......................................................................................................39
5.1 SERIAL MICROPROCESSOR INTERFACE BLOCK (BGA PACKAGE ONLY) ........................................... 39
F
IGURE
29. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 39
5.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 39
F
IGURE
30. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 39
5.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 40
5.1.3 ADDR[7:0] (SCLK1 - SCLK8)..................................................................................................................................... 40
5.1.4 R/W (SCLK9)............................................................................................................................................................... 40
5.1.5 DUMMY BITS (SCLK10 - SCLK16)............................................................................................................................ 40
5.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 40
5.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 40
F
IGURE
31. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 41
T
ABLE
9: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND
LOAD
= 10
P
F).................................. 41
5.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 42
T
ABLE
10: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
................................................................................................... 42
F
IGURE
32. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
.................................................................. 42
5.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43
T
ABLE
11: XRT83VSH28 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
THAT
EXHIBIT
CONSTANT
ROLES
IN
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
43
T
ABLE
12: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
.................................................................................................... 43
T
ABLE
13: M
OTOROLA
M
ODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................................... 44
5.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45
F
IGURE
33. I
NTEL
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
............................................ 46
T
ABLE
14: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
........................................................................................ 46
5.5 MOTOROLA MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................... 47
F
IGURE
34. M
OTOROLA
68K μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
............................ 48
T
ABLE
15: M
OTOROLA
68K M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
........................................................................ 48
T
ABLE
16: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
(ADDR[7:0]).................................................................................................... 49
T
ABLE
17: M
ICROPROCESSOR
R
EGISTER
C
HANNEL
D
ESCRIPTION
................................................................................................... 49
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
0
X
00
H
B
IT
D
ESCRIPTION
................................................................................................. 51
T
ABLE
19: C
ABLE
LENGTH
S
ETTING
................................................................................................................................................ 52
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
................................................................................................. 52
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
................................................................................................. 53
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
................................................................................................. 54
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
................................................................................................. 55
相關(guān)PDF資料
PDF描述
XRT83VSH28IB 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH314IB 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83VSH28ES 功能描述:外圍驅(qū)動器與原件 - PCI 8 CH E1 LIU SH (low cost version) RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH28IB 功能描述:接口 - 專用 8 Ch T1/E1 Framer RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT83VSH28IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 8 Channel 1.8V-3.3V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH28IB-F 制造商:Exar Corporation 功能描述:T1/E1 LIU IC
XRT83VSH314 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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