參數(shù)資料
型號： XRT83SH38IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA225
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù)： 6/78頁
文件大小： 606K
代理商： XRT83SH38IB
XRT83SH38
II
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
T
ABLE
7: T
IMING
S
PECIFICATIONS
FOR
TCLK/TPOS/TNEG.................................................................................................................. 29
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 29
T
ABLE
8: E
XAMPLES
OF
HDB3 E
NCODING
............................................................................................................................................ 29
T
ABLE
9: E
XAMPLES
OF
B8ZS E
NCODING
............................................................................................................................................. 29
4.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 30
T
ABLE
10: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
......................................................................................... 30
4.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 30
F
IGURE
19. TAOS (T
RANSMIT
A
LL
O
NES
) ............................................................................................................................................ 30
4.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 30
4.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 31
F
IGURE
20. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
..................................................................................................... 31
4.5.2 QRSS GENERATION.................................................................................................................................................. 31
T
ABLE
11: R
ANDOM
B
IT
S
EQUENCE
P
OLYNOMIALS
................................................................................................................................ 31
4.5.3 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 31
T
ABLE
12: S
HORT
H
AUL
L
INE
B
UILD
O
UT
.............................................................................................................................................. 31
4.5.4 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 32
F
IGURE
21. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
......................................................................................................................... 32
4.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 32
4.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 33
F
IGURE
22. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
......................................................................................... 33
5.0 T1/E1 APPLICATIONS .........................................................................................................................34
5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 34
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 34
F
IGURE
23. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
L
OCAL
A
NALOG
L
OOPBACK
................................................................................................ 34
5.1.2 REMOTE LOOPBACK................................................................................................................................................ 34
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
R
EMOTE
L
OOPBACK
.......................................................................................................... 34
5.1.3 DIGITAL LOOPBACK................................................................................................................................................. 35
F
IGURE
25. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
IGITAL
L
OOPBACK
........................................................................................................... 35
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 35
F
IGURE
26. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
UAL
L
OOPBACK
............................................................................................................... 35
5.2 LINE CARD REDUNDANCY ........................................................................................................................... 36
5.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS.................................................................................................... 36
5.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY.................................................................................. 36
F
IGURE
27. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
................................................ 36
5.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 37
F
IGURE
28. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
.................................................. 37
5.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 38
5.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 38
F
IGURE
29. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
N+1 R
EDUNDANCY
............................................................ 38
5.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY................................................................................................... 39
F
IGURE
30. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
N+1 R
EDUNDANCY
.............................................................. 39
5.3 POWER FAILURE PROTECTION .................................................................................................................. 40
5.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 40
5.5 NON-INTRUSIVE MONITORING .................................................................................................................... 40
F
IGURE
31. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
..................................................................... 40
6.0 MICROPROCESSOR INTERFACE ......................................................................................................41
6.1 SERIAL MICROPROCESSOR INTERFACE BLOCK .................................................................................... 41
F
IGURE
32. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
........................................................................ 41
6.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 41
F
IGURE
33. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
....................................................................................... 41
6.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 42
6.1.3 ADDR[7:0] (SCLK1 - SCLK8)..................................................................................................................................... 42
6.1.4 R/W (SCLK9)............................................................................................................................................................... 42
6.1.5 DUMMY BITS (SCLK10 - SCLK16)............................................................................................................................ 42
6.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 42
6.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 42
F
IGURE
34. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
....................................................................................... 43
T
ABLE
13: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND
LOAD
= 10
P
F) ...................................... 43
6.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 44
T
ABLE
14: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
.......................................................................................................... 44
F
IGURE
35. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
........................................................................ 44
6.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 45
T
ABLE
15: XRT83SH38 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
THAT
EXHIBIT
CONSTANT
ROLES
IN
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
45
T
ABLE
16: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................................................... 45
T
ABLE
17: M
OTOROLA
M
ODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
................................................................................................. 46
相關PDF資料
PDF描述
XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL216_06 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL216IB 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL28IV 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
相關代理商/技術參數(shù)
參數(shù)描述
XRT83SH38IB-F 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SL216 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL216_06 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL216ES 功能描述:外圍驅動器與原件 - PCI 16 CH E1 LIU SH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SL216IB 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59
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