參數(shù)資料
型號: XRT83SH38IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 25/78頁
文件大小: 606K
代理商: XRT83SH38IB
XRT83SH38
22
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
The XRT83SH38 has the ability to switch the internal termination to "High" impedance by programming
RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL
is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also
available to control the receive termination for all channels simultaneously. This hardware pin takes priority
over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the
state of this pin is ignored. See
Figure 6
for a typical connection diagram using the internal termination.
F
IGURE
6. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
3.1.2
CASE 2: Internal Termination With One External Fixed Resistor for All Modes
Along with the internal termination, a high precision external fixed resistor can be used to optimize the return
loss. This external resistor can be used for all modes of operation ensuring one bill of materials. There are
three resistor values that can be used by setting the RxRES[1:0] bits in the appropriate channel register.
Selecting the value for the external fixed resistor is shown in
Table 4
.
By default, RxRES[1:0] is set to "None" for no external fixed resistor. If an external fixed resistor is used, the
XRT83SH38 uses the parallel combination of the external fixed resistor and the internal termination as the
input impedance. See
Figure 7
for a typical connection diagram using the external fixed resistor.
N
OTE
:
Without the external resistor, the XRT83SH38 meets all return loss specifications. This mode was created to add
flexibility for optimizing return loss by using a high precision external resistor.
F
IGURE
7. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
O
NE
E
XTERNAL
F
IXED
R
ESISTOR
3.2
Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
T
ABLE
4: S
ELECTING
THE
V
ALUE
OF
THE
E
XTERNAL
F
IXED
R
ESISTOR
R
X
RES[1:0]
E
XTERNAL
F
IXED
R
ESISTOR
0h (00)
None
1h (01)
240
2h (10)
210
3h (11)
150
R
TIP
R
RING
XRT83SH38 LIU
1:1
Internal Impedance
Line Interface T1/E1/J1
One Bill of Materials
Receiver
Input
R
TIP
R
RING
XRT83SH38 LIU
1:1
Internal Impedance
Line Interface T1/E1/J1
R
R=240
, 210
, or 150
Receiver
Input
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