參數(shù)資料
型號: XRT83SH38IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 16/78頁
文件大?。?/td> 606K
代理商: XRT83SH38IB
XRT83SH38
13
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
MCLKT1
K1
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with accuracy better
than ±50ppm and duty cycle within 40% to 60%. MCLKT1 is used in the T1 mode.
N
OTE
:
All channels must operate at the same clock rate, either T1, E1 or J1. This
pin is internally pulled "Low" with a 50k
resistor.
MCLKE1
J1
I
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of
40% to 60% can be provided at this pin. In systems that have only one master clock
source available (E1 or T1), that clock should be connected to both MCLKE1 and
MCLKT1 inputs for proper operation.
N
OTE
:
All channels of the XRT83SH38 must be operated at the same clock rate,
either T1, E1 or J1. This pin is internally pulled “Low” with a 50k
resistor.
CLKSEL0
CLKSEL1
CLKSEL2
A8
B8
C8
I
Clock Select inputs for Master Clock Synthesizer
Hardware Mode Only
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be
used to generate a master clock from an external accurate clock source according to
the table below. MCLKRATE is automatically generated from the state of the
EQC[4:0] pins.
N
OTE
:
These pins are internally pulled “Low” with a 50k
resistor.
S
IGNAL
N
AME
BGA
L
EAD
#
T
YPE
D
ESCRIPTION
2048
2048
2048
1544
MCLKE1
kHz
8
16
16
56
8
56
64
64
128
256
256
128
2048
2048
1544
1544
MCLKT1
kHz
1544
X
X
X
1544
X
X
X
X
X
X
X
2048
1544
2048
CLKOUT/
kHz
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
0
1
1
CLKSEL0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
CLKSEL1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
CLKSEL2
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
1544
2048
X
X
2048
1544
0
1
0
1
MCLKRATE
1
0
1
0
0
1
0
1
1
0
1
0
0
1
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