參數資料
| 型號： | XRT83L34IVTR |
| 廠商： | Exar Corporation |
| 文件頁數： | 73/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標準包裝： | 750 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁當前第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
72
D3
NLCD_n
Network Loop-Code Detection:
This bit operates differently in the Manual or the Automatic
Network Loop-Code detection modes.
In the Manual Loop-Code detection mode, (NLCDE1 = “0”
and NLCDE0 = “1” or NLCDE1 = “1” and NLCDE0 = “0”) this
bit gets set to “1” as soon as the Loop-Up (“00001”) or Loop-
Down (“001”) code is detected in the receive data for longer
than 5 seconds. The NLCD bit stays in the “1” state for as long
as the chip detects the presence of the Loop-code in the
receive data and it is reset to “0” as soon as it stops receiving
it. In this mode, if the NLCD interrupt is enabled, the chip will
initiate an interrupt on every transition of the NLCD.
When the Automatic Loop-code detection mode, (NLCDE1
= “1” and NLCDE0 =”1”) is initiated, the state of the NLCD
interface bit is reset to “0” and the chip is programmed to mon-
itor the receive input data for the Loop-Up code. This bit is set
to a “1” to indicate that the Network Loop Code is detected for
more than 5 seconds. Simultaneously the Remote Loop-Back
condition is automatically activated and the chip is pro-
grammed to monitor the receive data for the Network Loop
Down code. The NLCD bit stays in the “1” state for as long as
the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up code. Remote Loop-Back is
removed if the chip detects the “001” pattern for longer than 5
seconds in the receive data.Detecting the “001” pattern also
results in resetting the NLCD interface bit and initiating an
interrupt provided the NLCD interrupt enable bit is active.
When programmed in Automatic detection mode, the
NLCD interface bit stays “High” for the entire time the Remote
Loop-Back is active and initiate an interrupt anytime the status
of the NLCD bit changes. In this mode, the Host can monitor
the state of the NLCD bit to determine if the Remote Loop-
Back is activated.
RO
0
D2
AISD_n
Alarm Indication Signal Detect: This bit is set to a “1” to indi-
cate All Ones Signal is detected by the receiver. The value of
this bit is based on the current status of Alarm Indication Signal
detector of channel n. If the AISDIE bit is enabled, any transi-
tion on this bit will generate an Interrupt.
RO
0
D1
RLOS_n
Receive Loss of Signal: This bit is set to a “1” to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal of channel n. If the
RLOSIE bit is enabled, any transition on this bit will generate
an Interrupt.
RO
0
D0
QRPD_n
Quasi-random Pattern Detection: This bit is set to a “1” to
indicate the receiver is currently in synchronization with QRSS
pattern. The value of this bit is based on the current status of
Quasi-random pattern detector of channel n. If the QRPDIE bit
is enabled, any transition on this bit will generate an Interrupt.
RO
0
TABLE 25: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| VI-B6H-MX-B1 | CONVERTER MOD DC/DC 52V 75W |
| IDT72V841L15PFI8 | IC FIFO SYNC 2048X18 15NS 64QFP |
| VI-22V-MY | CONVERTER MOD DC/DC 5.8V 50W |
| MS3106R28-15S | CONN PLUG 35POS STRAIGHT W/SCKT |
| VE-JNL-MX-S | CONVERTER MOD DC/DC 28V 75W |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT83L34IVTR-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38ES | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L38ES-BG | 功能描述:界面開發(fā)工具 Eval System for XRT83L38 Series RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
發(fā)布緊急采購，3分鐘左右您將得到回復。