參數(shù)資料
型號: XRT75VL00
廠商: Exar Corporation
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: E3/DS3/STS-1線路接口單元與抖動衰減器
文件頁數(shù): 48/50頁
文件大?。?/td> 268K
代理商: XRT75VL00
XRT75VL00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.3
46
8.2.3
With Remote loopback activated as shown in Figure 28,the receive data on RTIP and RRING is looped back
after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit
timing. The receive data is also output via the RPOS and RNEG pins.
During the remote loopback mode, if the jitter attenuator is selected in the transmit path, the receive data after
the Clock and Data Recovery Block is looped back to the transmit path and pass through the jitter attenuator
using RxClk as the transmit timing.
REMOTE LOOPBACK:
N
OTE
:
Input signals on TxClk, TPDATA and TNDATA are ignored during Remote loopback.
8.3
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS pins “High” or in Host mode
by setting the TAOS control bits to “1” in the Channel control registers. When the TAOS is set, the Transmit
Section generates and transmits a continuous AMI all “1’s” pattern on TTIP and TRING pins. The frequency of
this “1’s” pattern is determined by TClk.TAOS data path is shown in Figure 29.
TRANSMIT ALL ONES (TAOS):
F
IGURE
28. R
EMOTE
L
OOPBACK
F
IGURE
29. T
RANSMIT
A
LL
O
NES
(TAOS)
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
1
ENCODER
HDB3/B3ZS
1
DECODER
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or Transmit path
Tx
Rx
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or Transmit path
Tx
Rx
TAOS
Transmit All 1
1
1
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