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參數(shù)資料
| 型號： | XRT75VL00 |
| 廠商： | Exar Corporation |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| 中文描述： | E3/DS3/STS-1線路接口單元與抖動衰減器 |
| 文件頁數(shù)： | 41/50頁 |
| 文件大?。?/td> | 268K |
| 代理商： | XRT75VL00 |
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XRT75VL00
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
39
0x01
R/W
D0
DMOIE
Writing a “1” to this bit field enables the DMO inter-
rupt and triggers an interrupt when the transmitter
driver fails. Writing a “0” disables the interrupt.
0
D1
RLOSIE
Writing a “1” to this bit field enables the RLOS inter-
rupt and triggers an interrupt when the RLOS condi-
tion occurs. Writing a “0” disables the interrupt.
0
D2
RLOLIE
Writing a “1” to this bit field enables the RLOL inter-
rupt and triggers an interrupt when RLOL condition
occurs. Writing a “0” disables the interrupt.
0
D3
FLIE
Writing a “1” to this bit field enables the FL interrupt
and triggers an interrupt when the FIFO Limit of the
Jitter Attenuator is within 2 bits of overflow/underflow
condition. Writing a “0” disables the interrupt.
N
OTE
:
This bit field is ignored when the Jitter
Attenuator is disabled.
0
D4
PRBSIE
Writing a “1” to this bit enables the PRBS bit error
interrupt.
0
D5
CNT_SATIE
Writing a “1” to this bit enables the PRBS error-
counter saturation interrupt. When the PRBS error
counter reaches 0xFFFF, an interrupt will be gener-
ated.
0
0x02
Reset
Upon
Read
D0
DMOIS
This bit is set to “1” every time a DMO status change
has occurred since the last cleared interrupt.This bit
is cleared when read.
0
D1
RLOSIS
This bit is set to “1” every time a RLOS status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
0
D2
RLOLIS
This bit is set to “1” every time a RLOL status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
0
D3
FLIS
This bit is set to “1” every time a FIFO Limit status
change has occurred since the last cleared interrupt.
This bit is cleared when read.
0
D4
PRBSIS
This bit is set to “1” when a PRBS bit error is
detected. This bit is cleared when read.
0
D5
CNT_SATIS
This bit is set to “1” when the PRBS error counter has
saturated (0xFFFF). This bit is cleared when read.
0
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
A
DDRESS
(H
EX
)
T
YPE
B
IT
L
OCATION
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
(B
IN
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT75VL00IV | E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT79L71 | 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT79L71IB | 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
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| XRT79L72IB | 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75VL00_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75VL00D | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75VL00D_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET |
| XRT75VL00D1V-F | 制造商:Exar Corporation 功能描述: |
| XRT75VL00DES | 功能描述:時鐘合成器/抖動清除器 1CHT3/E3/STS1LIU+ DESYNC 3.3V DRV VER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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