參數(shù)資料
型號(hào): XRT75R12
廠商: Exar Corporation
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: 第十二章通道E3/DS3/STS-1線路接口單元與抖動(dòng)衰減器
文件頁(yè)數(shù): 66/89頁(yè)
文件大?。?/td> 457K
代理商: XRT75R12
XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
63
T
ABLE
22:
The above is:
C
HANNEL
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR97 (A
DDRESS
L
OCATION
= 0
X
61)
T
ABLE
23: C
HANNEL
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR225 (A
DDRESS
L
OCATION
= 0
X
E1)
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7, 6
Reserved
5
4
3
2
1
0
Channel 5 Interrupt Status
Channel 4 Interrupt Status
Channel 3 Interrupt Status
Channel 2 Interrupt Status
Channel 1 Interrupt Status
Channel 0 Interrupt Status
R/O
Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT75R12 has a
pending Channel n-related interrupt that is awaiting service. The
first six channels are serviced through this location and the other six
at address 0xE1. These two registers are used by the Host to iden-
tify the source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting
service.
1 - Indicates that there is at least one Channel n-related Interrupt
awaiting service. In this case, the user’s Interrupt Service routine
should be written such that the Microprocessor will now proceed to
read out the contents of the Source Level Interrupt Status Register -
Channel n (Address Locations = 0xn2) to determine the exact
source of the interrupt request.
N
OTE
:
Once this bit-field is set to "1", it will not be cleared back to
"0" until the user has read out the contents of the Source-
Level Interrupt Status Register bit, that corresponds to the
interrupt request channel.
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Reserved Reserved
Channel 11
Interrupt Status
Channel 10
Interrupt Status
Channel 9
Interrupt Status
Channel 8
Interrupt Status
Channel 7
Interrupt Status
Channel 6
Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
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