Each SUPER PATTERN consists" />
參數(shù)資料
型號: XRT75R03DIVTR
廠商: Exar Corporation
文件頁數(shù): 37/135頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標準包裝: 750
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-LQFP(14x20)
包裝: 帶卷 (TR)
XRT75R03D
127
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
CROSS-CHECKING OUR DATA
Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses.
The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
This amount to a period of (2160/51.84MHz) = 41,667ns.
In a period of 41, 667ns, the XRT75R03D (when configured to operate in the DS3 Mode), will output a total
(41,667ns x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE XRT75R03D
Whenever the XRT75R03D is configured to operate in a "SONET De-Sync" application, the device will accept
a continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the
corresponding data). The channel within the XRT75R03D (which will be configured to operate in the "DS3"
Mode) will output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter
Requirements - per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated below in Figure
65.
10.8.3
How does the XRT75R03D permit the user to comply with the SONET APS Recovery Time
requirements of 50ms (per Telcordia GR-253-CORE)?
Telcordia GR-253-CORE, Section 5.3.3.3 mandates that the "APS Completion" (or Recovery) time be 50ms or
less. Many of our customers interpret this particular requirement as follows.
FIGURE 64. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC
FIGURE 65. SIMPLE ILLUSTRATION OF THE XRT75R03D BEING USED IN A SONET DE-SYNCHRONIZER" APPLICA-
TION
PATTERN A
PATTERN B
DS3 to STS-N
Mapper/
Demapper
IC
DS3 to STS-N
Mapper/
Demapper
IC
XRT75R03D
STS-N Signal
TPDATA_n input pin
TCLK_n input
De-Mapped (Gapped)
DS3 Data and Clock
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