參數(shù)資料
型號: XRT75L02IVTR-F
廠商: Exar Corporation
文件頁數(shù): 1/50頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 2CH 100TQFP
標準包裝: 1,000
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 2/2
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
DECEMBER 2005
REV. 1.0.3
GENERAL DESCRIPTION
The XRT75L02 is a two-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates independent
Receivers, Transmitters and Jitter Attenuators in a
single 100 pin TQFP package.
The XRT75L02 can be configured to operate in either
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz) modes.The transmitter can be turned off (tri-
stated) for redundancy support and for conserving
power.
The XRT75L02’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L02 incorporates advanced crystal-less
jitter attenuators that can be selected either in the
transmit
or
receive
path.
The
jitter
attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications.
The XRT75L02 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L02 supports local,remote and digital
loop-backs. The XRT75L02 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
Detects and Clears LOS as per G.775.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
On-chip clock synthesizer generates the
appropriate rate clock from a single frequency
XTAL.
Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
Provides low jitter output clock.
TRANSMITTER:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitters can be turned on or off.
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator.
Jitter Attenuator can be selected in Receive or
Transmit paths.
16 or 32 bits selectable FIFO size.
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration.
Supports optional internal Transmit Driver
Monitoring.
PRBS error counter register to accumulate errors.
Hardware Mode for control and configuration.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V ± 5% power supply.
5 V Tolerant I/O.
Available in 100 pin TQFP.
-40°C to 85°C Industrial Temperature Range.
APPLICATIONS
E3/DS3 Access Equipment.
STS1-SPE to DS3 Mapper.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
Fiber Optic Terminals.
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