參數(shù)資料
型號(hào): XRT75R03DIV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: 14 X 20 MM, LQFP-128
文件頁(yè)數(shù): 6/134頁(yè)
文件大?。?/td> 803K
代理商: XRT75R03DIV
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)
XRT75R03D
REV. 1.0.2
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
III
THE PER-CHANNEL REGISTERS .......................................................................................................... 64
T
ABLE
22: C
HIP
R
EVISION
N
UMBER
R
EGISTER
- CR63 (A
DDRESS
L
OCATION
= 0
X
3F) ........................................ 64
T
ABLE
23: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75R03D 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC ................................................................................................................................. 64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS ................................................................... 66
T
ABLE
24: S
OURCE
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
01 .................. 66
T
ABLE
25: S
OURCE
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
02 .................. 68
T
ABLE
26: A
LARM
S
TATUS
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
03 ................................................ 70
T
ABLE
27: T
RANSMIT
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
04 ......................................... 75
T
ABLE
28: R
ECEIVE
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
05 ........................................... 78
T
ABLE
29: C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06 ......................................... 80
T
ABLE
30: J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07 ......................... 83
9.0 Diagnostic Features: ........................................................................................................................ 85
9.1 PRBS G
ENERATOR
AND
D
ETECTOR
: ................................................................................................................ 85
9.2 LOOPBACKS: ............................................................................................................................................... 85
9.2.1 ANALOG LOOPBACK: ....................................................................................................................... 85
Figure 26. PRBS MODE ................................................................................................................................. 85
Figure 27. Analog Loopback ........................................................................................................................... 86
9.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 87
9.2.3 REMOTE LOOPBACK: ....................................................................................................................... 87
Figure 28. Digital Loopback ............................................................................................................................ 87
Figure 29. Remote Loopback .......................................................................................................................... 87
9.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 88
10.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75R03D ............................................ 88
Figure 30. Transmit All Ones (TAOS) ............................................................................................................. 88
10.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................ 89
Figure 31. A Simple Illustration of a DS3 signal being mapped into and transported over the SONET Network
90
10.2 MAPPING/DE-MAPPING JITTER/WANDER .............................................................................................. 91
10.2.1 HOW DS3 DATA IS MAPPED INTO SONET .................................................................................... 91
Figure 32. A Simple Illustration of the SONET STS-1 Frame ......................................................................... 92
Figure 33. A Simple Illustration of the STS-1 Frame Structure with the TOH and the Envelope Capacity Bytes
Designated .................................................................................................................................... 93
Figure 34. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 94
Figure 35. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 95
Figure 36. Illustration of the Byte Structure of the STS-1 SPE ....................................................................... 96
Figure 37. An Illustration of Telcordia GR-253-CORE’s Recommendation on how map DS3 data into an STS-1
SPE ............................................................................................................................................... 97
Figure 38. A Simplified "Bit-Oriented" Version of Telcordia GR-253-CORE’s Recommendation on how to map
DS3 data into an STS-1 SPE ........................................................................................................ 97
10.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits .......................................... 98
Figure 39. A Simple Illustration of a DS3 Data-Stream being Mapped into an STS-1 SPE, via a PTE .......... 99
Figure 40. An Illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, when mapping in
a DS3 signal that has a bit rate of 44.736Mbps + 1ppm, into an STS-1 signal .......................... 100
10.3 J
ITTER
/W
ANDER
DUE
TO
P
OINTER
A
DJUSTMENTS
........................................................................................ 102
10.3.1 The Concept of an STS-1 SPE Pointer ......................................................................................... 102
Figure 41. An Illustration of the STS-1 SPE traffic that will be generated by the Source PTE, when mapping a
DS3 signal that has a bit rate of 44.736Mbps - 1ppm, into an STS-1 signal .............................. 102
Figure 42. An Illustration of an STS-1 SPE straddling across two consecutive STS-1 frames ..................... 103
10.3.2 Pointer Adjustments within the SONET Network ........................................................................ 104
Figure 43. The Bit-format of the 16-Bit Word (consisting of the H1 and H2 bytes) with the 10 bits, reflecting the
location of the J1 byte, designated ............................................................................................. 104
Figure 44. The Relationship between the Contents of the "Pointer Bits" (e.g., the 10-bit expression within the H1
and H2 bytes) and the Location of the J1 Byte within the Envelope Capacity of an STS-1 Frame ...
104
10.3.3 Causes of Pointer Adjustments .................................................................................................... 105
相關(guān)PDF資料
PDF描述
XRT75R03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03IV THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R03DIV-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3-Ch E3/DS3/STS-1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R03DIVTR 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03DIVTR-F 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT75R03ES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03IV 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray