參數(shù)資料
型號： XRT75L06DIB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PBGA217
封裝： 23 X 23 MM, BGA-217
文件頁數(shù)： 6/103頁
文件大小： 679K
代理商： XRT75L06DIB
XRT75L06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
xr
REV. 1.0.4
III
60
F
IGURE
41. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
.......................................................................................... 61
F
IGURE
42. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
.......................................................................................... 62
F
IGURE
43. I
LLUSTRATION
OF
THE
B
YTE
S
TRUCTURE
OF
THE
STS-1 SPE....................................................................................... 63
F
IGURE
44. A
N
I
LLUSTRATION
OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION
ON
HOW
MAP
DS3
DATA
INTO
AN
STS-1 SPE... 64
F
IGURE
45. A S
IMPLIFIED
"B
IT
-O
RIENTED
" V
ERSION
OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION
ON
HOW
TO
MAP
DS3
DATA
INTO
AN
STS-1 SPE ............................................................................................................................................................. 64
7.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS........................................... 65
F
IGURE
46. A S
IMPLE
I
LLUSTRATION
OF
A
DS3 D
ATA
-S
TREAM
BEING
M
APPED
INTO
AN
STS-1 SPE,
VIA
A
PTE.............................. 66
F
IGURE
47. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
"S
OURCE
" PTE,
WHEN
MAPPING
IN
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
+ 1
PPM
,
INTO
AN
STS-1
SIGNAL
............................................................... 67
F
IGURE
48. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
S
OURCE
PTE,
WHEN
MAPPING
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
- 1
PPM
,
INTO
AN
STS-1
SIGNAL
........................................................................... 69
7.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS.................................................................................. 69
7.3.1 THE CONCEPT OF AN STS-1 SPE POINTER............................................................................................................. 69
F
IGURE
49. A
N
I
LLUSTRATION
OF
AN
STS-1 SPE
STRADDLING
ACROSS
TWO
CONSECUTIVE
STS-1
FRAMES
.................................... 70
F
IGURE
50. T
HE
B
IT
-
FORMAT
OF
THE
16-B
IT
W
ORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
10
BITS
,
REFLECTING
THE
LOCATION
OF
THE
J1
BYTE
,
DESIGNATED
........................................................................................................................................ 71
F
IGURE
51. T
HE
R
ELATIONSHIP
BETWEEN
THE
C
ONTENTS
OF
THE
"P
OINTER
B
ITS
" (
E
.
G
.,
THE
10-
BIT
EXPRESSION
WITHIN
THE
H1
AND
H2
BYTES
)
AND
THE
L
OCATION
OF
THE
J1 B
YTE
WITHIN
THE
E
NVELOPE
C
APACITY
OF
AN
STS-1 F
RAME
............................... 71
7.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK.................................................................................... 71
7.3.3 CAUSES OF POINTER ADJUSTMENTS..................................................................................................................... 72
F
IGURE
52. A
N
I
LLUSTRATION
OF
AN
STS-1
SIGNAL
BEING
PROCESSED
VIA
A
S
LIP
B
UFFER
............................................................. 73
F
IGURE
53. A
N
I
LLUSTRATION
OF
THE
B
IT
F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"I"
BITS
DESIGNATED
.................................................................................................................................................................. 74
F
IGURE
54. A
N
I
LLUSTRATION
OF
THE
B
IT
-F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"D"
BITS
DESIGNATED
.................................................................................................................................................................. 75
7.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS ................................................................................. 76
7.4 CLOCK GAPPING JITTER................................................................................................................................ 76
F
IGURE
55. I
LLUSTRATION
OF
THE
T
YPICAL
A
PPLICATIONS
FOR
THE
LIU
IN
A
SONET D
E
-S
YNC
A
PPLICATION
.................................. 76
7.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR
DS3 APPLICATIONS ...................................................................................................................................... 77
T
ABLE
19: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
R
EQUIREMENT
PER
T
ELCORDIA
GR-253-CORE,
FOR
DS3
APPLICATIONS
.. 77
7.5.1 DS3 DE-MAPPING JITTER........................................................................................................................................... 78
7.5.2 SINGLE POINTER ADJUSTMENT............................................................................................................................... 78
F
IGURE
56. I
LLUSTRATION
OF
S
INGLE
P
OINTER
A
DJUSTMENT
S
CENARIO
......................................................................................... 78
7.5.3 POINTER BURST.......................................................................................................................................................... 78
F
IGURE
57. I
LLUSTRATION
OF
B
URST
OF
P
OINTER
A
DJUSTMENT
S
CENARIO
..................................................................................... 79
7.5.4 PHASE TRANSIENTS................................................................................................................................................... 79
F
IGURE
58. I
LLUSTRATION
OF
"P
HASE
-T
RANSIENT
" P
OINTER
A
DJUSTMENT
S
CENARIO
..................................................................... 79
7.5.5 87-3 PATTERN.............................................................................................................................................................. 80
F
IGURE
59. A
N
I
LLUSTRATION
OF
THE
87-3 C
ONTINUOUS
P
OINTER
A
DJUSTMENT
P
ATTERN
............................................................. 80
7.5.6 87-3 ADD....................................................................................................................................................................... 80
F
IGURE
60. I
LLUSTRATION
OF
THE
87-3 A
DD
P
OINTER
A
DJUSTMENT
P
ATTERN
................................................................................ 81
7.5.7 87-3 CANCEL................................................................................................................................................................ 81
F
IGURE
61. I
LLUSTRATION
OF
87-3 C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
................................................................................ 81
7.5.8 CONTINUOUS PATTERN............................................................................................................................................. 82
F
IGURE
62. I
LLUSTRATION
OF
C
ONTINUOUS
P
ERIODIC
P
OINTER
A
DJUSTMENT
S
CENARIO
................................................................ 82
7.5.9 CONTINUOUS ADD..................................................................................................................................................... 82
F
IGURE
63. I
LLUSTRATION
OF
C
ONTINUOUS
-A
DD
P
OINTER
A
DJUSTMENT
S
CENARIO
......................................................................... 83
7.5.10 CONTINUOUS CANCEL............................................................................................................................................. 83
F
IGURE
64. I
LLUSTRATION
OF
C
ONTINUOUS
-C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
................................................................... 83
7.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997...................................... 84
7.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION................................................................................................................................................. 84
7.7.1 INTRINSIC JITTER TEST RESULTS............................................................................................................................ 84
T
ABLE
20: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
T
EST
R
ESULTS
"
FOR
SONET/DS3 A
PPLICATIONS
..................................... 84
7.7.2 WANDER MEASUREMENT TEST RESULTS.............................................................................................................. 85
7.8 DESIGNING WITH THE LIU .............................................................................................................................. 85
7.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRINSIC
JITTER AND WANDER REQUIREMENTS.................................................................................................................... 85
F
IGURE
65. I
LLUSTRATION
OF
THE
LIU
BEING
CONNECTED
TO
A
M
APPER
IC
FOR
SONET D
E
-S
YNC
A
PPLICATIONS
.......................... 85
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06.................................................... 86
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E............................................ 86
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16 ............................................ 86
相關(guān)PDF資料
PDF描述
XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75L06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03DIV THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75L06DIB-F 功能描述:外圍驅(qū)動器與原件 - PCI 6-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L06ES 功能描述:時鐘合成器/抖動清除器 6 CHT3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L06IB 功能描述:接口 - 專用 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT75L06IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 6-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R03 制造商:EXAR 制造商全稱:EXAR 功能描述:THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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