參數(shù)資料
型號： XRT75L06DIB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PBGA217
封裝： 23 X 23 MM, BGA-217
文件頁數(shù)： 4/103頁
文件大?。?/td> 679K
代理商： XRT75L06DIB
XRT75L06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE OF CONTENTS
xr
REV. 1.0.4
I
GENERAL DESCRIPTION................................................................................................ 1
A
PPLICATIONS
............................................................................................................................................... 1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75L06D............................................................................................................................ 1
ORDERING INFORMATION.................................................................................................................... 1
F
EATURES
.................................................................................................................................................... 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
....................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
......................................................................................................... 2
F
IGURE
2. XRT75L06D
IN
BGA
PACKAGE
(B
OTTOM
V
IEW
) .............................................................................................................. 3
TABLE OF CONTENTS......................................................................................................
I
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
T
RANSMIT
I
NTERFACE
.................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
...................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
A
NALOG
P
OWER
AND
G
ROUND
.................................................................................................................... 12
DIGITAL
P
OWER
AND
G
ROUND
..................................................................................................................... 14
1.0 CLOCK SYNTHESIZER......................................................................................................................... 16
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
I
NPUT
C
LOCK
C
IRCUITRY
D
RIVING
THE
M
ICROPROCESSOR
...................................... 16
1.1 CLOCK DISTRIBUTION .................................................................................................................................... 16
F
IGURE
4. C
LOCK
D
ISTRIBUTION
C
ONGIFURED
IN
E3 M
ODE
W
ITHOUT
U
SING
SFM.......................................................................... 16
2.0 THE RECEIVER SECTION .................................................................................................................... 17
F
IGURE
5. R
ECEIVE
P
ATH
B
LOCK
D
IAGRAM
.................................................................................................................................... 17
2.1 RECEIVE LINE INTERFACE............................................................................................................................. 17
F
IGURE
6. R
ECEIVE
L
INE
I
NTERFACE
C
ONNECTION
.......................................................................................................................... 17
2.2 ADAPTIVE GAIN CONTROL (AGC) ................................................................................................................. 18
2.3 RECEIVE EQUALIZER...................................................................................................................................... 18
F
IGURE
7. ACG/E
QUALIZER
B
LCOK
D
IAGRAM
................................................................................................................................. 18
2.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS................................................................................................ 18
2.4 CLOCK AND DATA RECOVERY...................................................................................................................... 18
2.4.1 DATA/CLOCK RECOVERY MODE .............................................................................................................................. 18
2.4.2 TRAINING MODE.......................................................................................................................................................... 18
2.5 LOS (LOSS OF SIGNAL) DETECTOR.............................................................................................................. 19
2.5.1 DS3/STS-1 LOS CONDITION ....................................................................................................................................... 19
T
ABLE
1: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ............................................................................................................................................ 19
2.5.2 DISABLING ALOS/DLOS DETECTION ....................................................................................................................... 19
2.5.3 E3 LOS CONDITION:.................................................................................................................................................... 20
F
IGURE
8. L
OSS
O
F
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775............................................................................................ 20
F
IGURE
9. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775. ........................................................................................... 20
2.5.4 INTERFERENCE TOLERANCE.................................................................................................................................... 21
F
IGURE
10. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
DS3/STS-1................................................................................................ 21
F
IGURE
11. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3.............................................................................................................. 21
T
ABLE
2: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
........................................................................................................................... 22
2.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION:..................................................................................... 23
F
IGURE
12. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
................................................................................................. 23
2.6 B3ZS/HDB3 DECODER..................................................................................................................................... 23
3.0 THE TRANSMITTER SECTION............................................................................................................. 24
F
IGURE
13. T
RANSMIT
P
ATH
B
LOCK
D
IAGRAM
................................................................................................................................ 24
3.1 TRANSMIT DIGITAL INPUT INTERFACE ........................................................................................................ 24
F
IGURE
14. T
YPICAL
INTERFACE
BETWEEN
TERMINAL
EQUIPMENT
AND
THE
XRT75L06D (
DUAL
-
RAIL
DATA
)...................................... 24
F
IGURE
15. T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
........................................................................................................................ 25
F
IGURE
16. S
INGLE
-R
AIL
OR
NRZ D
ATA
F
ORMAT
(E
NCODER
AND
D
ECODER
ARE
E
NABLED
)............................................................ 25
3.2 TRANSMIT CLOCK ........................................................................................................................................... 26
3.3 B3ZS/HDB3 ENCODER..................................................................................................................................... 26
3.3.1 B3ZS ENCODING ......................................................................................................................................................... 26
F
IGURE
18. B3ZS E
NCODING
F
ORMAT
........................................................................................................................................... 26
3.3.2 HDB3 ENCODING......................................................................................................................................................... 26
F
IGURE
17. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER
AND
DECODER
ARE
DISABLED
)............................................................................. 26
F
IGURE
19. HDB3 E
NCODING
F
ORMAT
.......................................................................................................................................... 27
相關(guān)PDF資料
PDF描述
XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75L06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03DIV THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75L06DIB-F 功能描述:外圍驅(qū)動器與原件 - PCI 6-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L06ES 功能描述:時鐘合成器/抖動清除器 6 CHT3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L06IB 功能描述:接口 - 專用 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT75L06IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 6-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R03 制造商:EXAR 制造商全稱:EXAR 功能描述:THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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