參數(shù)資料
型號(hào)： XRT75L02IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 48/50頁(yè)
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 2CH 100TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
XRT75L02
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
REV. 1.0.3
5
30
TxClkINV/
SClk
I
Hardware Mode: Transmit Clock Invert
Host Mode: Serial Clock Input:
Function of this pin depends on whether the XRT75L02 is configured to operate
in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures all the Transmitters
to sample the TPOS_n and TNEG_n data on the rising edge of the TxClk_n .
NOTES:
1.
If the XRT75L02 is configured in HOST mode, this pin functions as
SClk input pin (please refer to the pin description for Microprocessor
interface).
82
TxMON
I
Transmitter Monitor:
When this pin is pulled “High”, MTIP and MRING are connected internally to
TTIP and TRING and allows self monitoring of the transmitter.
74
52
TxLEV_0
TxLEV_1
I
Transmit Line Build-Out Enable/Disable Select - Channel 0:
Transmit Line Build-Out Enable/Disable Select - Channel 1:
These input pins select the Transmit Line Build-Out circuit.
Setting these pins to "High" disables the Line Build-Out circuit of Channel n. In
this mode, Channel n outputs partially-shaped pulses onto the line via the
TTIP_n and TRing_n output pins.
Setting these pins to "Low" enables the Line Build-Out circuit of Channel n. In
this mode, Channel n outputs shaped pulses onto the line via the TTIP_n and
TRing_n output pins.
To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per
Bellcore GR-499-CORE or Bellcore GR-253-CORE:
1. Set these pins to "1" if the cable length between the Cross-Connect and the
transmit output of Channel is greater than 225 feet.
2. Set these pins to "0" if the cable length between the Cross-Connect and the
transmit output of Channel is less than 225 feet.
These pins are active only if the following two conditions are true:
a. The XRT75L02 is configured to operate in either the DS3 or SONET STS-1
Modes.
b. The XRT75L02 is configured to operate in the Hardware Mode.
NOTES:
1.
These pins are internally pulled down.
2.
If the XRT75L02 is configured in HOST mode, these pins should be
tied to GND.
75
51
TAOS_0
TAOS_1
I
Transmit All Ones Select - Channel 0:
Transmit All Ones Select - Channel 1:
A “High" on this pin causes the Transmitter Section of Channel_n to generate
and transmit a continuous AMI all “1’s” pattern onto the line. The frequency of
this “1’s” pattern is determined by TxClk_n.
NOTES:
1.
This input pin is ignored if the XRT75L02 is operating in the HOST
Mode and should be tied to GND.
2.
Analog Loopback and Remote Loopback have priority over request.
3.
This pin is internally pulled down.
TRANSMIT INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
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