參數(shù)資料
型號(hào)： XRT75L02IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 34/50頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 2CH 100TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
xr
XRT75L02
REV. 1.0.3
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
I
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
FEATURES ..................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................... 1
TRANSMIT INTERFACE CHARACTERISTICS ....................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ......................................................................................................... 2
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L02 .............................................................................................................................. 2
FIGURE 2. PIN OUT OF THE XRT75L02............................................................................................................................................ 3
ORDERING INFORMATION .................................................................................................................... 3
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
TRANSMIT INTERFACE .................................................................................................................................... 4
RECEIVE INTERFACE ...................................................................................................................................... 6
CLOCK INTERFACE......................................................................................................................................... 8
CONTROL AND ALARM INTERFACE........................................................................................................ 9
MODE SELECT............................................................................................................................................ 11
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)......................................................................... 11
JITTER ATTENUATOR INTERFACE .................................................................................................................. 12
ANALOG POWER AND GROUND .................................................................................................................... 13
DIGITAL
POWER AND GROUND...................................................................................................................... 13
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 15
TABLE 1: ABSOLUTE MAXIMUM RATINGS......................................................................................................................................... 15
TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................................................ 15
2.0 TIMING CHARACTERISTICS .............................................................................................................. 16
FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L02 (DUAL-RAIL DATA) .......................................... 16
FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING .......................................................................................................................... 16
FIGURE 5. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ................................................................................................... 17
FIGURE 6. TRANSMIT INTERFACE CIRCUIT FOR E3, DS3 AND STS-1 RATES .................................................................................... 17
3.0 LINE SIDE CHARACTERISTICS: ....................................................................................................... 18
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 18
FIGURE 7. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703......................................................................... 18
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ....................................................... 18
FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ............................ 19
TABLE 4: STS-1 PULSE MASK EQUATIONS ..................................................................................................................................... 19
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) .............................. 20
FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ..................................................................... 20
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 21
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 21
FIGURE 10. MICROPROCESSOR SERIAL INTERFACE STRUCTURE ..................................................................................................... 22
FIGURE 11. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 22
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) .................................. 23
4.0 THE TRANSMITTER SECTION: ......................................................................................................... 24
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 24
4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................ 24
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 24
FIGURE 12. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)............................................................ 24
FIGURE 13. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED) ............................................................................. 24
4.2.2 HDB3 ENCODING:...................................................................................................................................................... 25
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 25
FIGURE 14. B3ZS ENCODING FORMAT ........................................................................................................................................... 25
FIGURE 15. HDB3 ENCODING FORMAT .......................................................................................................................................... 25
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 26
4.3.2 INTERFACING TO THE LINE:.................................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 26
FIGURE 16. TRANSMIT DRIVER MONITOR SET-UP. ........................................................................................................................... 26
4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 27
5.0 THE RECEIVER SECTION: ................................................................................................................. 27
5.1 AGC/EQUALIZER: .......................................................................................................................................... 27
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 27
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