
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
PRELIMINARY
REV. P1.0.1
234
4.3.1
The purpose of the Receive DS3 LIU Interface block
is two-fold:
1.
To receive encoded digital data from the DS3 LIU
IC.
The Receive DS3 LIU Interface Block
2.
To decode this data, convert it into a binary data
stream and to route this data to the Receive DS3
Framer block.
Figure 80 presents a simple illustration of the Re-
ceive DS3 LIU Interface block.
The Receive Section of the XRT74L73 will via the Re-
ceive DS3 LIU Interface Block receive timing and da-
ta information from the incoming DS3 data stream.
The DS3 Timing information will be received via the
RxLineClk input pin and the DS3 data information will
be received via the RxPOS and RxNEG input pins.
The Receive DS3 LIU Interface block is capable of re-
ceiving DS3 data pulses in unipolar or bipolar format.
If the Receive DS3 framer is operating in the bipolar
format, then it can be configured to decode either
AMI or B3ZS line code data. Each of these input for-
mats and line codes will be discussed in detail, below.
4.3.1.1
Unipolar Decoding
If the Receive DS3 LIU Interface block is operating in
the Unipolar (single-rail) mode, then it will receive the
Single Rail NRZ DS3 data pulses via the RxPOS in-
put pin. The Receive DS3 LIU Interface block will al-
so receive its timing signal via the RxLineClk signal.
N
OTE
:
The RxLineClk signal will function as the timing
source for the entire Receive Section of the XRT74L73.
No data pulses will be applied to the RxNEG input
pin. The Receive DS3 LIU Interface block receives a
logic "1" when a logic "1" level signal is present at the
RxPOS pin, during the sampling edge of the RxLi-
neClk signal. Likewise, a logic "0" is received when a
logic "0" level signal is applied to the RxPOS pin.
Figure 81 presents an illustration of the behavior of
the RxPOS, RxNEG and RxLineClk input pins when
the Receive DS3 LIU Interface block is operating in
the Unipolar mode.
F
IGURE
80. A S
IMPLE
I
LLUSTRATION
OF
THE
R
ECEIVE
DS3 LIU I
NTERFACE
B
LOCK
RxPOS
RxNEG
RxLineClk
To Receive DS3
Framer Block
Receive DS3
LIU Interface
Block
F
IGURE
81. B
EHAVIOR
OF
THE
R
X
POS, R
X
NEG
AND
R
X
L
INE
C
LK
SIGNALS
DURING
DATA
RECEPTION
OF
U
NIPOLAR
D
ATA
RxPOS
RxNEG
RxLineClk
Data
1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1