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參數(shù)資料
| 型號： | XRT73LC03AIV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 61/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x20） |
| 包裝： | 托盤 |
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XRT73LC03A
7
REV. 1.0.4
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
96
REGR/
RxClkINV
I
Register Reset Input (Invert RxClk(n)) Output - Select:
The function of this pin depends upon whether the XRT73LC03A is oper-
ating in the HOST Mode or in the Hardware Mode.
NOTE: This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input:
Setting this input pin "Low" causes the XRT73LC03A to reset the con-
tents of the Command Registers to their default settings and default
operating configuration.
In the Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Chan-
nels in the XRT73LC03A to invert their RxClk_(n) clock output signals
and configures Channel (n) to output the recovered data via the
RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n).
Setting this pin "Low" configures Channel (n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
RECEIVE INTERFACE
PIN #NAME
TYPE
DESCRIPTION
CLOCK INTERFACE
PIN #NAME
TYPE
DESCRIPTION
47
99
103
EXClk_0
EXClk_1
EXClk_2
I
External Reference Clock Input - Channel (n):
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz
clock signal for DS3 applications or a 51.84 MHz clock signal for SONET
STS-1 applications.
The Channel (n) Clock Recovery PLL uses this signal as a Reference
Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The
Clock recovery PLL also generates the exact clock for the LIU.
It is permissible to use the same clock that drives the TxClk_(n) input
pin.
It is permissible to operate the three Channels at different data rates.
OPERATING MODE SELECT
PIN #NAME
TYPE
DESCRIPTION
93
SR/(DR)I
Receive Output Single-Rail/Dual-Rail Select:
Setting this pin "High" configures the Receive Sections of all Channels to
output data in a Single-Rail Mode to the Terminal Equipment.
Setting this pin "Low" configures the Receive Section of all Channels to
output data in a Dual-Rail Mode to the Terminal Equipment.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC03AIVF | 制造商:Exar Corporation 功能描述:Line Interface Unit 51.84Mbps DS3/E3/STS-1 Serial 120-Pin LQFP |
| XRT73LC03AIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 3-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73LC04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04AES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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