參數(shù)資料
型號(hào): XRT73LC00AIV
廠商: Exar Corporation
文件頁(yè)數(shù): 38/61頁(yè)
文件大?。?/td> 0K
描述: IC LIU STS1/DS3/E3 SGL 44TQFP
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
XRT73LC00A
40
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT
If the XRT73LC00A is operating in the HOST Mode, the state of ALOS can be polled or monitored by reading
in the contents of Command Register 0. The bit-format of Command Register 0 is presented below.
If the ALOS bit-field contains a “1”, the XRT73LC00A is currently declaring an ALOS condition. If the ALOS bit-
field contains a “0”, the device is NOT currently declaring an ALOS condition.
Disabling the ALOS Detector
It is useful to disable the ALOS Detector in the XRT73LC00A for debugging purposes. If the XRT73LC00A is
operating in the HOST Mode, the ALOS Detector can be disabled by writing a “1” into the ALOSDIS bit-field in
Command Register 2 as depicted below.
NOTE: Setting both the ALOSDIS and DLOSDIS bit-fields to “1” disables LOS Declaration in the XRT73LC00A.
2. The Digital LOS (DLOS) Declaration/Clearance Criteria
The XRT73LC00A declare a Digital LOS (DLOS) condition if the XRT73LC00A detects 160±32 or more
consecutive “0’s” in the incoming data.
The XRT73LC00A clears DLOS if it detects four consecutive sets of 32 bit-periods each of which contains at
least 10 “1’s” (e.g., average pulse density of greater than 33%).
Monitoring the State of DLOS
If the XRT73LC00A is operating in the HOST Mode, the state of DLOS can be polled or monitored by reading
in the contents of Command Register 0 as shown.
If the DLOS bit-field contains a “1”, the XRT73LC00A is currently declaring a DLOS condition. If the DLOS bit-
field contains a “0”, the device is NOT currently declaring the DLOS condition.
Disabling the DLOS Detector
COMMAND REGISTER CR0 (ADDRESS = 0X00)
D4
D3
D2
D1
D0
RLOL
RLOS
ALOS
DLOS
DMO
Read
Only
Read
Only
Read
Only
Read
Only
Read
Only
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
1
X
COMMAND REGISTER CR0 (ADDRESS = 0X00)
D4
D3
D2
D1
D0
RLOL
RLOS
ALOS
DLOS
DMO
Read
Only
Read
Only
Read
Only
Read
Only
Read
Only
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