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參數(shù)資料
| 型號(hào)： | XRT73L03IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 20 MM, HEAT SINK, TQFP-120 |
| 文件頁數(shù)： | 42/53頁 |
| 文件大小： | 604K |
| 代理商： | XRT73L03IV |
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XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
á
39
4.0
The XRT73L00 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes in
the chip:
Analog Local Loop-Back
Digital Local Loop-Back
Remote Loop-Back.
4.1
T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
When the XRT73L00 is configured to operate in the
Analog Local Loop-Back Mode, the XRT73L00 ig-
nores any signals that are input to the RTIP and
RRING input pins. The Transmitting Terminal Equip-
ment transmits clock and data into the XRT73L00 via
the TPDATA, TNDATA and TCLK input pins. This data
is processed through the Transmit Clock Duty Cycle
DIAGNOSTIC FEATURES OF THE XRT73L00
Adjust PLL and the HDB3/B3ZS Encoder. Finally,
this data outputs to the line via the TTIP and TRING
output pins and is looped back into the AGC/Receive
Equalizer Block. Consequently, this data is also pro-
cessed through the Receive Section of the
XRT73L00. After this post-loop-back data has been
processed through the Receive Section it outputs to
the Near-End Receiving Terminal Equipment via the
RPOS, RNEG, RCLK1 and RCLK2 output pins.
Figure 28 illustrates the path that the data takes when
the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT73L00 can be configured to operate in the
Analog Local Loop-Back Mode by employing either
one of the following two steps:
F
IGURE
27. T
HE
B
EHAVIOR
OF
THE
RPOS
AND
RCLK1 O
UTPUT
S
IGNALS
W
HILE
THE
XRT73L00
IS
T
RANSMITTING
S
INGLE
-R
AIL
D
ATA
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
RCLK1
RPOS
F
IGURE
28. T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
IN
THE
XRT73L00
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2
RPOS
RNEG
DR/SR
RLOS
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic
Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Analog Local
Loop-Back Path
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73LC00 | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC00IV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00 | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00A | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00AIV | E3/DS3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03IVS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT73L04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04B | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04BES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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