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參數(shù)資料
| 型號： | XRT7302 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 50/62頁 |
| 文件大?。?/td> | 715K |
| 代理商： | XRT7302 |
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
á
PRELIMINARY
REV. P1.1.6
46
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB(n) input pin “High"
and the RLB(n) input pin “Low".
N
OTE
:
The Analog Local Loop-Back mode does not work if
the transmitter is turned off via the TxOFF feature.
4.2
T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
.
When a given channel in the XRT7302 is configured
to operate in the Digital Local Loop-Back Mode, the
channel ignores any signals that are input to the RTIP
and RRing input pins. The Transmitting Terminal
Equipment transmits clock and data into the
XRT7302 via the TPData, TNData and TxClk input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder block. At this point, this data loops back to
the HDB3/B3ZS Decoder block. After this post-Loop-
Back data has been processed through the HDB3/
B3ZS Decoder block, it outputs to the Near-End Re-
ceiving Terminal Equipment via the RPOS, RNEG
and RxClk output pins.
Figure 28 illustrates the path the data takes in the
XRT7302 when the chip is configured to operate in
the Digital Local Loop-Back Mode.
To configure a channel to operate in the Digital Local
Loop-Back Mode, employ either one of the following
two-steps:
a. Operating in the HOST Mode
To configure Channel (n), write a “1" into both the
LLB and RLB bit-fields in Command Register CR4-
(n), as illustrated below.
b. Operating in the Hardware Mode
To configure Channel (n), pull both the LLB input pin
and the RLB input pin “High".
N
OTE
:
The Digital Local Loop-Back mode works even if the
transmitter is turned off via the TxOFF feature.
F
IGURE
28. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
PATH
IN
A
GIVEN
CHANNEL
OF
THE
XRT7302
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
RTIP(n)
RRing(n)
REQEN(n)
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
RLOL(n) EXClk(n)
Device
Monitor
MTIP(n)
MRing(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV(n)
TxOFF(n)
DMO(n)
TTIP(n)
TRing(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
Notes:
1. (n) = 0 or 1 for respective Channels
2. Serial Processor Interface input pins are shared by the two Channels in HOST Mode and redefined in Hardware Mode.
COMMAND REGISTER CR4-(N)
D4
D3
D2
D1
D0
X
STS-1/DS3_Ch(n) E3_Ch(n) LLB(n)
RLB(n)
X
X
X
1
1
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