參數(shù)資料
型號(hào)： XRT7302
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述： 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元）
文件頁(yè)數(shù)： 13/62頁(yè)
文件大?。?/td> 715K
代理商： XRT7302
á
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.6
9
42
REGR/
(RxClkNV)
I
Register Reset Input pin (Invert RxClk(n)) Output - Select):
The function of this pin depends upon whether the XRT7302 is operating in
the HOST Mode or in the Hardware Mode.
N
OTE
:
This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input pin:
Setting this input pin "Low" causes the XRT7302 to reset the contents of the
Command Registers to their default settings and default operating configura-
tion.
In the Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Channels in
the XRT7302 to invert their RxClk(n) clock output signals and configures
Channel (n) to output the recovered data via the RPOS(n) and RNEG(n) out-
put pins on the falling edge of RxClk(n).
Setting this pin "Low" configures Channel (n) to output the recovered data via
the RPOS(n) and RNEG(n) output pins on the rising edge of RxClk(n).
43
GND
****
ExClk Reference GND
44
VDD
****
ExClk Reference VDD
45
EXClk1
I
External Reference Clock Input - Channel 1:
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock sig-
nal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 appli-
cations.
The Clock Recovery PLL in Channel 1 uses this signal as a Reference Signal
for Declaring and Clearing the Receive Loss of Lock Alarm.
N
OTES
:
1. It is permissible to use the same clock which is also driving the TxClk
input pin.
2. It is permissible to operate the two Channels at different data rates
46
RLOL1
O
Receive Loss of Lock Output Indicator - Channel 1:
This output pin toggles "High" if Channel 1 of the XRT7302 has detected a
Loss of Lock Condition. Channel 1 declares an LOL (Loss of Lock) Condition
if the recovered clock frequency deviates from the Reference Clock frequency
(available at the EXClk(n) input pin) by more than 0.5%.
47
LCV1
O
Line Code Violation Indicator - Channel 1:
Whenever the Receive Section of Channel 1 detects a Line Code Violation, it
pulses this output pin "High". This output pin remains "Low" at all other times.
N
OTE
:
The XRT7302 outputs an NRZ pulse via this output pin. It is advisable
to sample this output pin via the RxClk1 clock output signal.
48
RLOS1
O
Receive Loss of Signal Output Indicator - Channel 1:
This output pin toggles "High" if Channel 1 in the XRT7302 has detected a
Loss of Signal Condition in the incoming line signal.
The criteria the XRT7302 uses to declare an LOS Condition depends upon
whether it is operating in the E3 or STS-1/DS3 Mode.
49
DGND
****
Receive Digital Ground - Channel 1
PIN DESCRIPTION
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
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