參數(shù)資料
型號： XRT72L73
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 27/105頁
文件大小： 1307K
代理商： XRT72L73
á
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.1
27
L24
L25
L26
RxPLOF_0
RxPLOF_1
RxPLOF_2
O
Receive PLCP—“Loss of Frame” Output Indicator:
The Receive PLCP Processor will assert this pin, when it declares a “Loss of
Frame” condition. This output will be negated when the Receive PLCP Processor
reaches the “In Frame” Condition.
N
OTE
:
This output pin is only active if the user has configured the XRT72L73 to
operate in the “ATM UNI” Mode.
T26
T23
R24
RxPOHFrame_0
RxPOHFrame_1
RxPOHFrame_2
O
Receive PLCP Frame Path Overhead (POH) Byte Serial Output Port—Begin-
ning of Frame Signal Pin:
This output pin, along with RxPOH, RxPOHClk, and RxPOHIns pins comprise the
“Receive PLCP Frame POH Byte” serial output port. This output pin provides fram-
ing information to external circuitry receiving and processing this POH (Path Over-
head) data, by pulsing “High” when the first bit of the Z6 byte is output via the
RxPOH output pin. This pin is “Low” at all other times during this PLCP POH fram-
ing cycle.
N
OTE
:
This output pin is only active if the XRT72L73 has been configued to oper-
ate in the “ATM UNI” Mode.
Receive PLCP “Out of Frame” Indicator:
The Receive PLCP Processor will assert this pin, when it declares an “Out of
Frame” condition. This output will be negated when the Receive PLCP Processor
reaches the “In Frame” Condition.
N
OTE
:
This output pin is only active if the user has configured the XRT72L73 to
operate in the “ATM UNI” Mode.
Receiver Red Alarm Indicator—Receive PLCP Processor:
The UNI asserts this output pin to denote that one of the following events has been
detected by the Receive PLCP Processor:
OOF—Out of Frame Condition
LOF—Loss of Frame Condition
N
OTE
:
This output pin is only active whenever the XRT72L73 has been configured
to operate in the “ATM UNI” Mode.
V25
V26
V23
RxPOOF_0
RxPOOF_1
RxPOOF_2
O
K24
K25
K26
RxPRed_0
RxPRed_1
RxPRed_2
O
Tx Cell Processor
AC16
AE17
AF17
TxCellTxed_0
TxCellTxed_1
TxCellTxed_2
O
Transmit Cell Processor—Cell Transmitted Indicator:
This output pin pulses “High” each time the Transmit Cell Processor transmits a
cell to the Transmit PLCP Processor (or Transmit DS3 Framer).
This output pin is only active if the XRT72L73 has been configured to operate in
the “ATM UNI” Mode.
Transmit GFC Nibble-Field Serial Input Port:
This signal, along with TxGFCClk and TxGFCMSB combine to function as the
“Transmit GFC Nibble-field” serial input port. The user will specify the value of the
GFC field, within a given ATM cell, by serial transmitting its four bit value into this
input. Each of these four bits will be clocked into the UNI via rising edge of the
TxGFCClk clock output signal.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L73 has
been configured to operate in the “Clear-Channel-Framer” Mode.
Transmit GFC Nibble Field Serial Input Port Clock:
This signal, along with TxGFC, and TxGFCMSB combine to function as the “Trans-
mit GFC Nibble-field” serial input port. The “Transmit GFC Nibble-field” serial input
port uses this output clock signal to sample the values applied to the TxGFC pin,
on its rising edge. This pin will provide four rising edges for each cell being trans-
mitted.
N
OTE
:
This output pin is only active whenever the XRT72L73 has been configured
to operate in the “ATM UNI” Mode.
AD7
AE7
AF7
TxGFC_0
TxGFC_1
TxGFC_2
I
AF5
AE6
AF6
TxGFCClk_0
TxGFCClk_1
TxGFCClk_2
O
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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