參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 30/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
30
156
TxGFCClk
O
Transmit GFC Nibble Field Serial Input Port Clock:
This signal, along with
TxGFC, and TxGFCMSB combine to function as the “Transmit GFC Nibble-
field” serial input port. The “Transmit GFC Nibble-field” serial input port uses
this output clock signal to sample the values applied to the TxGFC pin, on its
rising edge. This pin will provide four rising edges for each cell being transmit-
ted.
N
OTE
:
This output pin is only active whenever the XRT72L71 has been con-
figured to operate in the “ATM UNI” Mode.
157
ALE_AS
I
Address Latch Enable/Address Strobe:
This input is used to latch the
address (present at the Microprocessor Interface Address Bus, A[8:0]) into the
UNI Microprocessor Interface circuitry and to indicate the start of a READ/
WRITE cycle. This input is active-"High" in the Intel Mode (MOTO = “Low”)
and active-”Low” in the Motorola Mode (MOTO = “High”).
158
TxGFC
I
Transmit GFC Nibble-Field Serial Input Port:
This signal, along with TxG-
FCClk and TxGFCMSB combine to function as the “Transmit GFC Nibble-
field” serial input port. The user will specify the value of the GFC field, within a
given ATM cell, by serial transmitting its four bit value into this input. Each of
these four bits will be clocked into the UNI via rising edge of the TxGFCClk
clock output signal.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
159
GND
***
Ground Signal Pin
160
RDY_DTCK
O
READY or DTACK:
This active-”Low” output pin will function as the READY
output, when the microprocessor interface is running in the “Intel” Mode; and
will function as the DTACK output, when the microprocessor interface is running
in the “Motorola” Mode.
“Intel” Mode—READY Output.
When the UNI negates this output pin (e.g.,
toggles it “Low”), it indicates (to the
μ
P) that the current READ or WRITE
cycle is to be extended until this signal is asserted (e.g., toggled “High”).
“Motorola” Mode:—DTACK (Data Transfer Acknowledge) Output.
The
UNI Framer will assert this pin in order to inform the local microprocessor that
the present READ or WRITE cycle is nearly complete. If the UNI Framer
requires that the current READ or WRITE cycle be extended, then the UNI will
delay its assertion of this signal. The 68000 family of
μ
Ps requires this signal
from its peripheral devices, in order to quickly and properly complete a READ
or WRITE cycle.
PIN DESCRIPTION (CONTINUED)
P
IN
N
O
.
S
YMBOL
T
YPE
D
ESCRIPTION
相關PDF資料
PDF描述
XRT72L73 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT72L71IQ 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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