參數(shù)資料
型號(hào)： XRT71D00IQ-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 0K
描述： IC JITTER ATTENUATOR SGL 32TQFP
標(biāo)準(zhǔn)包裝： 250
類型： *
PLL： 是
輸入： 時(shí)鐘
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 3:2
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 44.736MHz
除法器/乘法器： 無(wú)/無(wú)
電源電壓： 3.135 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 托盤(pán)
á
XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
14
1.3.1
Jitter Tolerance:
The jitter tolerance in the network element is defined
as the maximum amount of jitter in the incoming sig-
nal that it can receive in an “error-free”manner.
1.3.2
Jitter Generation:
Jitter generation is defined in Section 7.3.3 of GR-
499-CORE. Jitter generation criteria exists for both
Category I and II interfaces, which consist of “map-
ping” and “pointer adjustment” jitter generation.
Mapping jitter is the sum of the intrinsic payload map-
ping jitter and the jitter that is generated as a result of
the bit stuffing mechnisms used in all of the asynchro-
nous DSn mapping into STS SPE.
1.3.3
Jitter Attenuation:
A digital Jitter Attenuation loop combined with the
FIFO provides Jitter attenuation. The Jitter Attenuator
requires no external components except for the refer-
ence clock.
Data is clocked into the FIFO with the associated
clock signal (TClk or RClk) and clocked out of the
FIFO with the dejittered clock and data. When the
FIFO is within 2 bits of being completely full, the FIFO
Limit (FL) will be set.
In Figure 5 and Figure 6, this “de-jittered” clock is la-
beled “Smoothed Clock”. This “Smoothed Clock” is
now used to “Read Out” the “Recovered Data” from
the 16/32 bit FIFO. This “Smoothed Clock” will also
be output to the Terminal Equipment via the “RRClk”
output pin. Likewise, the “Smoothed Recovered Data”
will output to the Terminal Equipment via the RRPOS
and RRNEG output pins.
The XRT71D00 device is designed to work as a com-
panion device with XRT73L00 (STS-1/DS3/E3) Line
Interface Unit.
ETSI TBR24 specifies the maximum output jitter in
loop timing must be no more than 0.4UIpp when mea-
sured between 100Hz to 800KHzwith upto 1.5UI input
jitter at 100Hz. This means a jitter attenuator with
bandwidth less than 100Hz is required to be compli-
ant with the standard. ITU G.751 is another applica-
tion where low bandwidth jitter attenuator is needed
to smooth the gapped clock output in the de-multi-
plexer system.
1.4
XRT71D00 JITTTER TRANSFER CHARACTERIS-
TICS
Table 1 and Table 2 summarizes the results of jitter
transfer characteristics testing, performed on the
FIGURE 7. CATEGORY 1 DS3 JITTER TRANSFER MASK
0.1
Jitter
Gain
(dB)
Acceptable
Range
40
Frequency (Hz)
slope = -20 dB/decade
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