參數(shù)資料
型號： XRT71D00IQ-F
廠商： Exar Corporation
文件頁數(shù)： 6/26頁
文件大小： 0K
描述： IC JITTER ATTENUATOR SGL 32TQFP
標(biāo)準(zhǔn)包裝： 250
類型： *
PLL： 是
輸入： 時鐘
輸出： 時鐘
電路數(shù)： 1
比率 - 輸入:輸出： 3:2
差分 - 輸入:輸出： 無/無
頻率 - 最大： 44.736MHz
除法器/乘法器： 無/無
電源電壓： 3.135 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 托盤
XRT71D00
á
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
13
The XRT71D00 DS3/E3/STS-1 Jitter Attenuator IC
consists of the following functional blocks:
Jitter Attenuator Phase Locked Loop(PLL)
Timing Control
2-Channel 16/32 Bit FIFO.
Microprocessor Serial Interface
1.0
THE JITTER ATTENUATOR PLL
The Jitter Attenuator PLL is a narrow-band PLL that
accepts a “jittery” clock signal via the RCLK input pin.
The Jitter Attenuator PLL locks onto the RCLK input
signal and synthesizes a “same-rate” signal. As the
Jitter Attenuator PLL synthesizes this signal, it elimi-
nates much of the jitter that exists within the RCLK in-
put signal. The resulting smoothed clock signal is
then output via the “RRCLK” output signal.
1.1
THE JITTER TRANSFER CHARACTERISTICS OF THE
JITTER ATTENUATOR PLL
The Jitter Transfer Characteristics of the XRT71D00
device is ultimately dictated by the Jitter Transfer
Characteristics of the Jitter Attenuator PLL. The Jitter
Transfer Characteristics of the Jitter Attenuator PLL is
dictated by the following variables.
1. The operating mode/data rate of the XRT71D00
device.
2. The setting of the BWS (Bandwidth Select) input
pin or bit-field.
1.2
DEFINITION OF JITTER
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as “short term
variations of the significant instants of a digita signal
from their ideal positions in time”. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.3
JITTER TRANSFER CHARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
FIGURE 6. ILLUSTRATION OF THE XRT71D00 (CONFIGURED TO OPERATE IN THE “HOST” MODE)
HOST/HW
Reset
16/32 Bit FIFO
Microprocessor Serial
Interface
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRClk
RRPOS
RRNEG
FL
RClk
RPOS
RNEG
ICT
CS
SDI
SDO
SClk
MClk
Smoothed
Clock
Jittery Clock
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參數(shù)描述
XRT71D00IQTR-F 功能描述:時鐘合成器/抖動清除器 DS3/E3/STS-1Jit Attn 3.3/5.0V 1 CH 1 CHIP RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT71D03 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
XRT71D03ES 功能描述:時鐘合成器/抖動清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT71D03IV 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
XRT71D03IV-F 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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