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| 型號(hào)： | XRT16L2552 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| 中文描述： | 2.25V至5.5V的杜阿爾特16字節(jié)FIFO |
| 文件頁數(shù)： | 9/47頁 |
| 文件大?。?/td> | 413K |
| 代理商： | XRT16L2552 |
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xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
9
2.9
The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup.
Table 3
and
Table 4
summarize the operating behavior for the transmitter and receiver. Also see
Figure 18
through
Figure 23
.
INTA and INTB Ouputs
2.10
The L2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
Crystal Oscillator or External Clock Input
T
ABLE
2: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
P
INS
FCR
BIT
-0=0
(FIFO D
ISABLED
)
FCR B
IT
-0=1 (FIFO E
NABLED
)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B 0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
T
ABLE
3: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
FCR B
IT
-0 = 0
(FIFO D
ISABLED
)
FCR B
IT
-0 = 1
(FIFO E
NABLED
)
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = at least 1 byte in FIFO
1 = FIFO empty
T
ABLE
4: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
FCR B
IT
-0 = 0
(FIFO D
ISABLED
)
FCR B
IT
-0 = 1
(FIFO E
NABLED
)
INTA/B Pin
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
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