Rev. 2.00 SERIAL INTERFACE READ BACK The readback function is used to view the content of the serial interface registers as well as" />
參數(shù)資料
型號： XRD98L61AIV-F
廠商： Exar Corporation
文件頁數(shù)： 8/38頁
文件大小： 0K
描述： IC CCD DIGITIZER 12BIT 48TQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 12
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
XRD98L61
16
Rev. 2.00
SERIAL INTERFACE READ BACK
The readback function is used to view the content of
the serial interface registers as well as several key
registers in the calibration logic. Readback is enabled
by writing a 1 to the RBenable bit of the Readback
register, bit D9 of register 62.
In the readback mode, the content of the selected
register is output on the 10 MSBs of the ADC output
bus pins DB[11:2]. As long as valid clocks and CCD
signal are applied, the calibration will continue to
function properly during readback (internally the ADC
data is still sent to the calibration logic).
RBenable RBreg
8
RBreg
7
RBreg
6
RBreg
5
Rbreg
4
RBreg
3
RBreg
2
RBreg
1
RBreg
0
Selected Register
0
x
none (ADC data output)
1
0
Gain
1
0
1
Offset
1
0
1
0
Calibration
1
0
1
Wait A
1
0
1
0
Wait B
1
0
1
0
1
OB Lines
1
0
1
0
CDAC
1
0
1
FDAC
1
0
1
0
Control
1
0
1
0
1
Polarity
1
0
1
0
1
0
Clock
1
0
1
0
1
Delay A
1
0
1
0
Delay B
1
0
1
0
1
DAC0
1
0
1
0
DAC1
1
0
1
0
ReadBack
1
0
1
Reset
1
0
1
x
FDAC output from Cal. logic
1
0
1
0
x
CDAC output from Cal. logic
1
0
1
x
Avg. output from Cal logic
Table 2. Read-back Register Selection
Registers are selected for readback by writing to the
RBreg[8:0] bits in the Readback register, bits D8 to D0
of register 62. If RBreg[8:6]=000, then RBreg[5:0] are
used to address the serial interface registers. Currently
only register addresses 0 to 14, 62 and 63 are defined.
If RBreg[8:6]
≠000, then RBreg[5:0] are ignored and
RBreg[8:6] are used to address registers in the calibra-
tion logic. Currently only three calibration registers are
accessible.
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