參數(shù)資料
型號(hào): XRD98L59AIGTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 2/37頁(yè)
文件大?。?/td> 0K
描述: IC CCD DIGITIZER 10BIT 28TSSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.6 V
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
XRD98L59
10
Rev. 2.00
D7
D6
D5
D4
D3
D2
D1
D0
Gain[7:0]
0 0 0 0 0 0 0 0 minimum gain (6 dB) *
1 1 1 1 1 1 1 1 maximum gain (38 dB)
Table 2. Gain Register bit assignment (Address 0000)
D7
D6
D5
D4
D3
D2
D1
D0
not used
Offset[5:0]
0 0 0 0 0 0 Do not use (00h)
0 0 0 0 0 1 Do not use (01h)
0 0 0 0 1 0 minimum offset (02h)
1 0 0 0 0 0 default offset (20h) *
1 1 1 1 1 1 maximum offset (3Fh)
Table 3. Target Offset Register bit assignment (Address 0001) for PGA
D7
D6
D5
D4
D3
D2
D1
D0
SBLK delay[2:0]
SPIX delay[2:0]
Exar test
0 0 0 min delay *
0 0 default
1 1 1 max delay
01, 10, 11 do not use
Table 4. Delay Register bit assignment (Address 0010)
D7
D6
D5
D4
D3
D2
D1
D0
not used
RST rej
Exar test
CLAMP opt
SBLK pol
SPIX pol
CLAMP pol
CAL pol
0 switch ON*
0 default
0 Cal only
0 active low* 0 active low* 0 active low* 0 active low*
1 clocked
1 do not use
1 Clamp+Cal* 1 active high 1 active high 1 active high 1 active high
Table 5. Clock Register bit assignment (Address 0011) for SPIX or SBLK
D7
D6
D5
D4
D3
D2
D1
D0
not used
Delay test
ADCIN
PD
OE
0 test off *
0 convert *
0 outputs off
1 test on
1 power down 1 outputs on *
Table 6. Control Register bit assignment (Address 0100)
Table 7. Calibration Register bit assignment (Address 0101)
D7
D6
D5
D4
D3
D2
D1
D0
not used
Cal Hold
Speed Up
DNS1
DNS0
Man DAC
0 cal active*
0 Speed Up off
0 DNS off
0 = Wide*
0 automatic*
1 hold value
1 Speed Up on*
1 DNS on*
1 = Narrow
1 manual
Note: * Shading indicates default values after power up or reset. The XRD98L59 does not reset the registers to default
va
lue after PD.
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