- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10747 > XRD98L59AIGTR-F (Exar Corporation)IC CCD DIGITIZER 10BIT 28TSSOP PDF資料下載
參數(shù)資料
| 型號： | XRD98L59AIGTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 15/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD DIGITIZER 10BIT 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
XRD98L59
22
Rev. 2.00
The ADC input node can be accesed for test purposes
using the ADCIN mode (SDI address 0100). Use the
following procedure to enable the ADCIN mode:
1) In the Serial interface Clock register, set the
Clamp Opt bit low (D4).
2) In the Serial interface Control register, set the
ADCIN bit high (D2).
3) Clock SBLK & SPIX to generate internal
ADC_CLK signal.
4) Apply ADC input signal to CCDin.
In this test mode the analog signal, Vin, applied to CCDin
pin will be converted by the ADC. The ADC output code
is related to Vin by the following rules:
1)
For Vin < VRB, ADC output code = 0,
2)
For Vin > VRT, ADC output code = 1023,
3)
For VRB < Vin < VRT, ADC output code = 1024
x (Vin - VRB) / (VRT - VRB)
CONTROL & RESET REGISTERS
ADCIN Bit
This bit activates a switch that connects CCDin directly
to the ADC input. In this mode, the PGA output is
disabled. See the ADC section for details.
PD Bit (Power Down)
This bit is used to put the chip in the Power Down mode.
It has the same effect as the PD pin. When the PD bit
is high the chip will go into the power down mode, all
conversions stop. When the PD bit is low the chip is in
its normal active mode. In the Power Down mode the
digital output pins are forced to the high impedance mode
and the ADC reference is disconnected. The serial
interface pins remain active in the Power Down mode.
OE Bit (Output Enable)
The ADC digital output bus is equipped with a high
impedance capability. When the OE bit is high the digital
outputs are enabled (active). When the OE bit is low the
digital outputs are in the high impedance mode (not
active). The OE bit only controls the digital output
drivers, all other circuits on the chip will remain active.
RESET Bit
This bit is used to reset all internal registers to default
values. This includes all the serial interface registers as
well as the registers in the calibration logic. To reset the
chip write a “1” to the reset bit. The reset bit will clear itself
after an internal delay, so there is no need to write a “0”
to the reset bit. The chip also has a Power-On-Reset
function (POR) so it will always power up with default
values in all registers.
It is recommended that the
XRD98L59 be reset after power is cycled to avoid loading
potentially incorrect serial port data from other ASICs in
the system.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9141EKA+T | IC COMPARATOR R-R SGL SOT23-8 |
| XRD9818ACGTR-F | IC 16B CCD/CIS SIG PROC 28TSSOP |
| AD73311ARZ-REEL | IC PROCESSOR FRONT END LP 20SOIC |
| AD73311ARSZ-REEL | IC ANALOG FRONT END 20-SSOP |
| MAX9109EUT+T | IC COMPAR LP SGL SOT23-6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L61 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61_01 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRD98L61EVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board for XRD98L61AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。