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參數(shù)資料
| 型號(hào)： | XRD9853 |
| 廠商： | Exar Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 75K |
| 代理商： | XRD9853 |
XRDAN103
4
Rev. 1.00
Figure 4. CDS - Black Reference Phase: RSTCCD Switch Closed
During the video phase of each pixel the SPIX switches are closed several nano-seconds after
the sampling edge of SHP. The difference between the pixel black reference level and video
level is transmitted through capacitors C1 & C2. Differential amplifier PGA1 amplifies both
CDS inputs from IN-POS and IN-NEG. The sampling edge of SHD turns off the SPIX
switches, storing the differential pixel value on capacitors C3 & C4.
+
PGA1
-
Vbias~0.8
External
Coupling
Capacitors
va
Vdd
CLAMP
SDRK
In_Pos
In_Neg
Gain
Register
to ADC
code
from
ADC
RSTCCD
C
C
D
GND
Vout
C1
C2
C3
Internal Capacitors
(~5pf)
+
PGA2
-
+
BUF
-
vc
vb
C4
SPIX
Enable_CAL
Offset
Calibration
+
PGA1
-
Vbias~0.8
External
Coupling
Capacitors
va
Vdd
CLAMP
SDRK
In_Pos
In_Neg
Gain
Register
to ADC
code
from
ADC
RSTCCD
C
C
D
GND
Vout
C1
C2
C3
Internal Capacitors
(~5pf)
+
PGA2
-
+
BUF
-
vc
vb
C4
SPIX
Enable_CAL
Offset
Calibration
Figure 5. CDS - Video Phase: SDRK Switches Open, SPIX Switches Closed
During the black reference phase of each pixel the RSTCCD switches are turned on, allowing
the difference between the black reference level voltage and Vdd to develop across
capacitors C1 and C2. The sampling edge of SHP opens the SDRK switches, sampling/
holding the black reference voltage across capacitors C1 & C2.
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