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參數(shù)資料
| 型號： | XRD9853 |
| 廠商： | Exar Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 75K |
| 代理商： | XRD9853 |
XRDAN103
3
Rev. 1.00
+
PGA1
-
Vbias~0.8
External
Coupling
Capacitors
va
Vdd
CLAMP
SDRK
In_Pos
In_Neg
Gain
Register
to ADC
code
from
ADC
RSTCCD
C
C
D
GND
Vout
C1
C2
C3
Internal Capacitors
(~5pf)
+
PGA2
-
+
BUF
-
vc
vb
C4
SPIX
Enable_CAL
Offset
Calibration
Figure 2. Block Diagram of the CDS
During the reset phase of each pixel the RSTCCD switches are turned off, see Figure 3,
opening the XRD9853 CDS input. This is done to limit the amount of reset pulse transients
seen by the front end of the XRD9853. SDRK switch is closed holding the inputs to PGA 1
to V
DD
.
Figure 3. CDS - Reset Phase: RSTCCD Switch is Open, SDRK Switch Closed
+
PGA1
-
Vbias~0.8
External
Coupling
Capacitors
va
Vdd
CLAMP
SDRK
In_Pos
In_Neg
Gain
Register
to ADC
code
from
ADC
RSTCCD
C
C
D
GND
Vout
C1
C2
C3
Internal Capacitors
(~5pf)
+
PGA2
-
+
BUF
-
vc
vb
C4
SPIX
Enable_CAL
Offset
Calibration
IN_POS (CDS non-inverting input) should be connected, via a capacitor, to the CCD
“Common” voltage. This is typically CCD ground, but could also be the V
of the CCD or a
CCD Reference output. IN_NEG (CDS inverting input) should be connected, via a capacitor,
to the CCD output signal. The external coupling capacitors on INPOS and INNEG should be
matched values (0.01
μ
f +/-10%).
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XRD9853AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA, and 10-bit A/D |
| XRD9855 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 10-Bit A/D |
| XRD9855AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 10-Bit A/D |
| XRD9856 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 10-Bit A/D |
| XRD9856AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 10-Bit A/D |
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