參數(shù)資料
型號(hào)： XRD9836ACG
廠商： Exar Corporation
文件頁(yè)數(shù)： 22/32頁(yè)
文件大小： 0K
描述： IC 16B CCD/CIS SIG PROC 48TSSOP
產(chǎn)品變化通告： Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝： 39
位數(shù)： 16
通道數(shù)： 3
功率（瓦特）： 500mW
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
封裝/外殼： 48-TSSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 48-TSSOP
包裝： 管件
xr
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
29
APPLICATION NOTES AND SCHEMAT-
ICS
See Figure 23 for a typical CCD application hookup.
The diagram shows an interface to a standard 3
channel output CCD. Both the ADC Output and OGI
Control are parallel interfaces to the system ASIC
controller. The timing inputs are provided by the sys-
tem ASIC or timing generator (TG). The serial port
control is typically sourced from a micro processor or
the system ASIC.
It is recommended that all AGND, DGND and OGND
pins, be connected to the analog ground plane under
the XRD9836. All VDD’s should be supplied from a
low noise, well filtered regulator which derives the
power supply voltage from the CCD power supply. All
of the AVDD pins are analog power supplies and
should be decoupled locally to the nearest ground pin
with at 0.1uF, high frequency capacitor. The DVDD
and OVDD power pins should be locally decoupled to
the nearest ground pin also. DVDD and OVDD should
be connected to the same power supply network as
the digital ASCI which receives data from the
XRD9836.
The XRD9836 has an input range limitation of 1V
maximum for a CCD input. If the maximum CCD out-
put signal swing is greater than 1V, a resisitive divider
network on the inputs can be used to reduce the CCD
output to meet the 1V input max requirement of the
XRD9836 inputs. See Figure 24 for a typical imple-
mentation of a resistor divider. Each input channel will
require a matching divider network.
FIGURE 23. TYPICAL CCD APPLICATION DIAGRAM FOR THE XRD9836
RED+
RED-
GRN+
GRN-
BLU+
BLU-
REXT
10K
ADCCLKK
VSAMP
BSAMP
LCLMP
LOAD
SCLK
SDIO
CCD
15V
A
G
N
D
A
G
N
D
A
G
N
D
G
N
D
O
G
N
D
O
G
N
D
A
V
D
A
V
D
A
V
D
V
D
O
V
D
O
V
D
VDD3A
VDD3D
TG
(timing generator)
ASIC
ADCO0
ADCO1
ADCO2
ADCO3
ADCO4
ADCO5
ADCO6
ADCO7
ADC
OUTPUT
BUS
OGI9
OGI8
OGI7
OGI6
OGI5
OGI4
OGI3
OGI2
OGI1
OGI0
IE
ASIC
OGI
CONTROL
9836
0.1uf
1uf
It is recommended that each
power pin be decoupled to
ground with capacitors placed
as close to power pin as
possible.
1nf
CAPP
CAPN
CMREF
2.2uf
0.1uf
2.2uf
0.1uf
2.2uf
0.1uf
2.2uf
0.1uf
FIGURE 24. INPUT RESISTIVE DIVIDER NETWORK
1nf
CCD
15V
XRD9836
RED+
RED -
1nf
C1
C2
R1
R2
V
sig
V
in
V
sig
V
in =
(R1/(R1+R2))
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