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參數(shù)資料
| 型號(hào)： | XRD9818EVAL |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 3/28頁(yè) |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XRD9818 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
11
3.0
REGISTER MAP
Note:
* Exar test bits, do not over write the default values.
Shaded cells represent unused bits.
3.1
PGA Gain Registers
There are three PGA registers for individually programming the gain in the RED, GREEN, and BLUE channels.
Each gain register has 9 bits of resolution. Bits D[9:1] control the gain while bit D0 is N/A (don’t care).
The
XRD9818 has two gain ranges to help interface to imagers that have 3V or 2V of output signal swing. The GS
bit, located in the MODE 1 register, defaults to GS=0 for a gain of 1x to 5x or if GS=1 the gain would be 1.5x to
7.5x. The gain range of 1 to 5x (GS=0) is intended for use with imagers that have a 3V output swing, while the
gain range 1.5 to 7.5x is intended for imagers with 2V or less of output swing. The coding for the PGA registers
is straight binary. See “Section 4.3, Programmable Gain” on page 20 for a functional description of the
XRD9818’s gain stage.
* Power-on default value
INTERNAL REGISTER MAP
Register
Name
Address
Data Bits
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RED Gain
0
msb
lsb
GREEN Gain
0
1
msb
lsb
BLUE Gain
0
1
0
msb
lsb
RED Offset
0
1
COR[1] COR[0] FOR[7] FOR[6] FOR[5] FOR[4] FOR[3] FOR[2] FOR[1] FOR[0]
GREEN Offset
0
1
0
COG[1] COG[0] FOG[7] FOG[6] FOG[5] FOG[4] FOG[3] FOG[2] FOG[1] FOG[0]
BLUE Offset
0
1
0
1
COB[1] COB[0] FOB[7] FOB[6] FOB[5] FOB[4] FOB[3] FOB[2] FOB[1] FOB[0]
MODE 1
0
1
0
CH[2]
CH[1]
CH[0]
GS
LC
CCDEN
B/N
C/R[2]
C/R[1]
C/R[0]
MODE 2
0
1
PD
OE
Lpol
ADCpol
Bpol
Vpol
BSAMPDelay
1
0
BL[4]
BL[3]
BL[2]
BL[1]
BL[0]
BT[4]
BT[3]
BT[2]
BT[1]
BT[0]
VSAMPDelay
1
0
1
VL[4]
VL[3]
VL[2]
VL[1]
VL[0]
VT[4]
VT[3]
VT[2]
VT[1]
VT[0]
ADCLKDelay
1
0
1
0
A[4]
A[3]
A[2]
A[1]
A[0]
DO[4]
DO[3]
DO[2]
DO[1]
DO[0]
TEST
1
0
1
*
RESET/RB
1
Reset
READ
RB[3]
RB[2]
RB[1]
RB[0]
GAIN REGISTER SETTINGS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (V/V)
msb
lsb
N/A
w/GS bit = 0*
w/GS bit = 1
000000000*
…
111111111
not
used
1x
…
5x
1.5x
…
7.5x
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