REV. 1.0.3 SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU" />
參數(shù)資料
型號： XR19L400IL40-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 44/46頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L202 40QFN
標(biāo)準包裝： 1
系列： *
XR19L400
7
REV. 1.0.3
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L400 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 4.
FIGURE 4. XR19L400 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
UART
Channel A
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
INT
ACP
RESET
PWRSAVE
ACP
PWRSAVE
A0
A1
A2
IOR#
IOW#
CS#
VCC3.3
VCC5.0
TX+
RX+
TX-
RX-
GND
RS-485 Interface
UART_ CS#
IOW#
IOR#
UART_ INT
UART_ RESET
R_EN
D0
D1
D2
D3
D4
D5
D6
D7
Intel Data Bus Interconnections
UART
Channel A
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
ACP
RESET
PWRSAVE
ACP
PWRSAVE
A0
A1
A2
VCC3.3
VCC5.0
TX+
RX+
TX-
RX-
GND
RS-485 Interface
UART_ RESET
R_EN
D0
D1
D2
D3
D4
D5
D6
D7
Motorola Data Bus Interconnections
IOR#
VCC
IOW#
R/W#
CS#
UART_ CS #
UART_INT
INT
VCC
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