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參數(shù)資料
| 型號： | XR19L400IL40-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 18/46頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR19L202 40QFN |
| 標準包裝： | 1 |
| 系列： | * |
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XR19L400
25
REV. 1.0.3
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
]
TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Ready)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xoff character)
-
0
1
None (default) or Wake-up Indicator
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition) or the device has come out of sleep mode.
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 7).
ISR[4]: Xoff Character Interrupt Status (requires EFR bit-4=1)
This bit is enabled when IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff
character(s).
ISR[5]: Reserved
For normal operation, this bit should remain a logic 0.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, and set the transmit/receive FIFO trigger levels.
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR19L400IL40-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR19L400IL40TR-F | 功能描述:UART 接口集成電路 Transceiver 1 Tx/1 Rx RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR19L402 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER |
| XR19L402_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER |
| XR19L402IL48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER |
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