參數資料
| 型號： | XR19L212IL48-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 13/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART/TXRX RS232 48QFN |
| 標準包裝： | 260 |
| 特點： | * |
| 通道數： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 3.3 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 托盤 |
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XR19L212
20
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
2.18.1.2
UART active, charge pump of RS-232 transceiver shut down
If the ACP pin is HIGH and the UART portion of the L212 is not in sleep mode, then the charge pump will
automatically shut down to conserve power if the following conditions are true:
■ no activity on the TXD output signal
■ modem input signals (RX, CTS) are LOW
■ modem inputs have been idle for approximately 30 seconds
When these conditions are satisfied, the L212 shuts down the charge pump and tri-states the RS-232 drivers
to conserve power. In this mode, the RS-232 receivers are fully active and the internal registers of the L212
can be accessed. The time for the charge pump to resume normal operation after exiting the sleep mode is
typically 45
s. It will wake up by any of the following:
■ a receive data start bit transition on the RXD input (LOW to HIGH)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a LOW to HIGH transition on any of the modem or general purpose serial inputs
Because the receivers are fully active when the charge pump is turned off, any data received will be transferred
to/from the UART without any issues.
2.18.2
Full Sleep Mode
In full sleep mode, the L212 shuts down the charge pump and the internal oscillator. The L212 enters the full
sleep mode if the following conditions are satisfied:
■ the UART portion of the L212 is already in sleep mode (no output on XTAL2)
■ the ACP (Autosleep for Charge Pump) pin is HIGH
When these conditions are satisfied, both the UART and the charge pump will be in the sleep mode. In this
mode, the RS-232 receivers are fully active and the internal registers of the L212 can be accessed. The L212
exits the full sleep mode if either the ACP pin becomes LOW or the internal oscillator starts up. The time for the
charge pump to resume normal operation after exiting the full sleep mode is typically 45
s.
2.18.3
Power-Save Feature
This mode is in addition to the sleep mode and in this mode, the core logic of the L212 is isolated from the CPU
interface. If the address lines, data bus lines, IOW#, IOR# and CS# remain steady when the L212 is in full
sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 41. However, if the input lines are floating or are toggling while the L212 is in sleep
mode, the current can be up to 100 times more. If not using the Power-Save feature, an external buffer would
be required to keep the address and data bus lines from toggling or floating to achieve the low current. But if
the Power-Save feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an
external buffer by internally isolating the address, data and control signals from other bus activities that could
cause wasteful power drain (see Figure 1). The L212 enters Power-Save mode when this pin is connected to
VCC, and the UART portion of the L212 is already in sleep mode.
Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by:
■ a receive data start bit transition, or
■ a change of logic state on any of the modem or general purpose serial inputs: i.e., any of the MSR bits 0-
3 shows a ’1’
The L212 will return to the Power-Save mode automatically after a read to the MSR (to reset the modem
inputs) and all interrupting conditions have been serviced and cleared. The L212 will stay in the Power-Save
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the Power-Save pin is connected to
GND.
If the L212 is awakened by any one of the above conditions, it issues an interrupt as soon as the oscillator
circuit is up and running and the device is ready to transmit/receive. This interrupt has the same encoding (bit-
0 of ISR register = 1) as "no interrupt pending" and will clear when the ISR register is read. This will show up in
the ISR register only if no other interrupts are enabled.
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