REV. 1.0.2 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 4.7 Receiver The receiver section contains an 8-bit" />
參數(shù)資料
型號： XR17V258IV-0A-EVB
廠商： Exar Corporation
文件頁數(shù)： 38/69頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V258 144LQFP
標準包裝： 1
系列： *
XR17V258
43
REV. 1.0.2
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
4.7
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits [4:1]. Upon unloading the receive data byte from RHR, the receive FIFO
pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches
the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out
function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths
as defined by LCR bits [1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit [0].
4.7.1
Receiver Operation in non-FIFO Mode
FIGURE 17. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X Clock
(8XMODE Register)
Receive Data Characters
Data Bit
Validation
Error
Flags in
LSR bits
4:2
4.7.2
Receiver Operation with FIFO
FIGURE 18. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Sampling
Clock (8XMODE Reg.)
E
rro
rFl
ags
(64
-set
s)
E
rro
rFl
ags
in
LS
R
bi
ts
4:
2
64 bytes by 11-
bit wide FIFO
Receive Data Characters
FIFO Trigger=48
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Data fills to 56
Data falls to 40
Data Bit
Validation
Receive Data
FIFO
(64-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# re-asserts when data falls below
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
相關PDF資料
PDF描述
GCC10DRYN-S734 CONN EDGECARD 20POS DIP .100 SLD
VI-B1Y-EV CONVERTER MOD DC/DC 3.3V 99W
155880-000 SOLDER SLEEVE 11MM DIA SHIELD
VI-2VR-EX CONVERTER MOD DC/DC 7.5V 75W
VI-2VP-EX CONVERTER MOD DC/DC 13.8V 75W
相關代理商/技術參數(shù)
參數(shù)描述
XR17V258IVF 制造商:Exar Corporation 功能描述:
XR17V258IV-F 功能描述:UART 接口集成電路 66MHz Octal PCI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17V258IVTR-F 功能描述:UART 接口集成電路 66MHz Octal PCI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17V352 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUAL PCI EXPRESS UART
XR17V352IB-0A-EVB 功能描述:界面開發(fā)工具 Eval Board for XR17V352IB Series RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*