XR17V252
13
REV. 1.0.2
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
TABLE 5: XR17V252 UART AND DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS
MEMORY SPACE
READ/WRITE
DATA WIDTH
COMMENT
0x000 - 0x00F
UART channel 0 Regs
(
8/16/24/32
First 8 regs are 16550 compatible
0x010 - 0x07F
Reserved
0x080 - 0x093
DEVICE CONFIGURA-
TION REGISTERS
8/16/24/32
0x094 - 0x0FF
Reserved
0x100
UART 0 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x100
UART 0 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x140 - 0x17F
Reserved
0x180 - 0x1FF
UART 0 – Read FIFO
with errors
Read-Only
16/32
64 bytes of RX FIFO data + LSR
0x200 - 0x20F
UART channel 1 Regs
(
8/16//24/32
First 8 regs are 16550 compatible
0x210 - 0x2FF
Reserved
d
0x300
UART 1 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x300
UART 1 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x340 - 0x37F
Reserved
0x380 - 0x3FF
UART 1 – Read FIFO
with errors
Read-Only
16/32
64 bytes of RX FIFO data + LSR