參數(shù)資料
型號(hào)： XR17V252IM-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 33/69頁(yè)
文件大小： 0K
描述： IC UART PCI BUS DUAL 100TQFP
標(biāo)準(zhǔn)包裝： 90
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
XR17V252
39
REV. 1.0.2
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
4.7.2
Receiver Operation with FIFO
5.0
UART CONFIGURATION REGISTERS
5.1
Receive Holding Register (RHR) - Read only
5.2
Transmit Holding Register (THR) - Write only
5.3
Baud Rate Generator Divisors (DLM, DLL and DLD)
The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver. The rate is
programmed through registers DLM, DLL and DLD which are only accessible when LCR bit [7] is set to logic 1.
details.
5.4
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
5.4.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR bit [0] = a logic 1) and receive interrupts (IER bit [0] = logic 1) are enabled, the
RHR interrupts (see ISR bits [4:3]) status will reflect the following:
A.
The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B.
FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C.
The receive data ready bit (LSR bit [0]) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
FIGURE 18. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Sampling
Clock (8XMODE Reg.)
E
rror
Fl
ag
s
(64-s
ets)
E
rro
rFl
ags
i
n
LS
R
bi
ts
4:2
64 bytes by 11-
bit wide FIFO
Receive Data Characters
FIFO Trigger=48
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Data fills to 56
Data falls to 40
Data Bit
Validation
Receive Data
FIFO
(64-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# re-asserts when data falls below
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR17V252IMTR-F 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 3.3V 100-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR17V252IMTR-F
XR17V254 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
XR17V254_08 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
XR17V254IV 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
XR17V254IV-0A-EVB 功能描述:UART 接口集成電路 Supports V254 144 ld LQFP,PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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