參數(shù)資料
型號： XR17C158
廠商： Exar Corporation
英文描述： PCI Bus Octal UART(八通用異步接收器/發(fā)送器（滿足通訊系統(tǒng)中PCI總線和高帶寬要求）)
中文描述： PCI總線八路的UART（八通用異步接收器/發(fā)送器（滿足通訊系統(tǒng)中的PCI總線和高帶寬要求））
文件頁數(shù)： 34/51頁
文件大?。?/td> 685K
代理商： XR17C158
PCI BUS OCTAL UART
XR17C158
PRELIMINARY
REV. 1.0.0
34
FCR BIT-0: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO. (de-
fault).
Logic 1 = Enable the transmit and receive FIFOs.
This bit must be set to logic 1 when other FCR bits
are written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive
FIFO
reset. (default)
Logic 1 = Reset the receive FIFO pointers and FIFO
level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset. (default)
Logic 1 = Reset the transmit FIFO pointers and FIFO
level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins
are not available in this device. It is provided for lega-
cy software.
Logic 0 = Set DMA to mode 0. (default)
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits
by selecting one of the four tables. The 4 user select-
able trigger levels in 4 tables are supported for com-
patibility reasons. These 2 bits set the trigger level for
the transmit FIFO interrupt. The UART will issue a
transmit interrupt when the number of characters in
the FIFO falls below the selected trigger level, or
when it gets empty in case that the FIFO did not get
filled over the trigger level on last re-load.
Table 13
below shows the selections.
FCR[7:6]: Receive FIFO Triggeer Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits.
These 2 bits are used to set the trigger level for the
receiver FIFO interrupt.
Table 13
shows the complete
selections.
T
ABLE
13: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCTR
B
IT
-7
FCTR
B
IT
-6
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
R
ECEIVE
T
RIGGER
L
EVEL
T
RANSMIT
T
RIGGER
L
EVEL
C
OMPATIBILITY
0
0
0
0
1
1
0
1
0
1
0
0
1 (default)
4
8
14
1 (default)
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
24
28
16
8
24
30
Table-B. 16C650A compatible.
1
0
0
0
1
1
X
0
1
0
1
X
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
Table-C. 16C654 compatible.
1
1
X
X
Programmable Programmable Table-D. 16C850, 16c2850,
16C2852, 16C854, 16C864,
16C872 compatible.
相關PDF資料
PDF描述
XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
XR17D152CM UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
XR17D152IM UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
XR17D158IV UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
相關代理商/技術參數(shù)
參數(shù)描述
XR17C158CV 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CV-0A-EVB 功能描述:UART 接口集成電路 Supports C158 144 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CV-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CVTR-F 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C158CVTR-F
XR17C158IV 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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