參數(shù)資料
型號: XR17C158
廠商: Exar Corporation
英文描述: PCI Bus Octal UART(八通用異步接收器/發(fā)送器(滿足通訊系統(tǒng)中PCI總線和高帶寬要求))
中文描述: PCI總線八路的UART(八通用異步接收器/發(fā)送器(滿足通訊系統(tǒng)中的PCI總線和高帶寬要求))
文件頁數(shù): 24/51頁
文件大?。?/td> 685K
代理商: XR17C158
PCI BUS OCTAL UART
XR17C158
PRELIMINARY
REV. 1.0.0
24
4.3
Each UART in the 158 includes the infrared encoder
and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The input pin ENIR conve-
niently activates all 8 UART channels to start up in
the infrared mode. This global control pin enables the
MCR bit-6 funtion in every UART channel register. Af-
ter power up or a reset, the software can overwrite
MCR bit-6 if so desired. ENIR and MCR bit-6 also
disable its receiver while the transmitter is sending
data. This prevents the echoed data from going to the
receiver. The global activation ENIR pin prevents the
infrared emitter from turning on and drawing large
amount of current while the system is starting up.
I
NFRARED
M
ODE
When the infrared feature is enabled, the transmit da-
ta outputs, TX[7:0], would idle at logic zero level.
Likewise, the RX [7:0] inputs assume an idle level of
logic zero.
The infrared encoder sends out a
3/16 of a bit wide
pulse for each “0” bit in the transmit data stream. This
signal encoding reduces the on-time of the infrared
LED, hence reduces the power consumption. See
Figure 10
below.
The infrared decoder receives the input pulse from
the infrared sensing diode on RX pin. Each time it
senses a light pulse, it returns a logic zero to the data
bit stream. The RX input signal may be inverted prior
F
IGURE
9. A
UTO
RTS/DTR
AND
CTS/DSR F
LOW
C
ONTROL
O
PERATION
The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit
shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA
re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next re-
ceive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB#
and CTSA# controlling the data flow.
RTSA#
CTSB#
RXA
TXB
Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON
OFF
ON
Suspend
Restart
9
RTS High
Threshold
Data Starts
ON
OFF
ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data
RTS Low
Threshold
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#
CTSA#
RXB
TXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
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