REV. 1.0.2 MCR[3]: OP2# Output If OP2# is selected as the MF# output, then this bit contr" />
參數(shù)資料
型號(hào)： XR16V2652IL-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 24/48頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR V2652 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V2652
30
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
REV. 1.0.2
MCR[3]: OP2# Output
If OP2# is selected as the MF# output, then this bit controls the state of this general purpose output.
Logic 0 = OP2# output set HIGH(default).
Logic 1 = OP2# output set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 12.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1)
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2652 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4=1)
Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be idling LOW. SEE”INFRARED MODE” ON
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1)
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
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