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參數資料
| 型號： | XR16V2652IL-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數： | 23/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR V2652 32QFN |
| 標準包裝： | 1 |
| 系列： | * |
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XR16V2652
3
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
32-QFN
PIN #
44-PLCC
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
7
6
3
15
14
10
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
9
8
7
6
5
4
3
2
I/O
Data bus lines [7:0] (bidirectional).
IOR#
14
24
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
11
20
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CS#
10
18
I
UART chip select (active low). This function selects channel A or B in
accordance with the logical state of the CHSEL pin. This allows data to
be transferred between the user CPU and the V2652.
CHSEL
8
16
I
Channel Select - UART channel A or B is selected by the logical state
of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects
the UART channel B while a logic 1 selects UART channel A. Normally,
CHSEL could just be an address line from the user CPU such as A4.
Bit-0 of the Alternate Function Register (AFR) can temporarily override
CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially
useful during the initialization routine.
INTA
21
34
O
UART channel A Interrupt output (active high). A HIGH indicates chan-
nel A is requesting for service. For more details, see
INTB
9
17
O
UART channel B Interrupt output (active high). A HIGH indicates chan-
nel B is requesting for service. For more details, see
TXRDYA#
-
1
O
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
TXRDYB#
-
32
O
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
MODEM OR SERIAL I/O INTERFACE
TXA
23
38
O
UART channel A Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XR16V2652IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO |
| XR16V2652IL-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16V2652ILTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 32Byte FIFO 2.5V/3.3V 32-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR16V2652ILTR-F |
| XR16V2750 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR16V2750_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
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