參數(shù)資料
型號： XR16L788CQ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： HIGH PERFORMANCE OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù)： 24/42頁
文件大小： 557K
代理商： XR16L788CQ
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XR16L788 OCTAL UART
REV. 1.1.4
24
MSR is by any of the MSR bits, 0, 1, 2 and 3.
Receive Xon
/
Xoff/Special character is by detection
of a Xon, Xoff or Special character.
CTS#/DSR# is by a change of state on the input pin
with auto flow control enabled, EFR bit-7, and
depending on selection on MCR bit-2.
RTS#/DTR# is when its receiver changes the state
of the output pin during auto RTS/DTR flow control
enabled by EFR bit-6 and selection of MCR bit-2.
4.11.2 Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR regis-
ter.
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
RXRDY and RXRDY Time-out are cleared by read-
ing data until FIFO falls below the trigger level.
TXRDY interrupt is cleared by a read to the ISR
register.
MSR interrupt is cleared by a read to the MSR reg-
ister.
Xon, Xoff or Special character interrupt is cleared
by a read to ISR.
RTS#/DTR# and CTS#/DSR# status change inter-
rupts are cleared by a read to the MSR register.
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR con-
tents may be used as a pointer to the appropriate in-
terrupt service routine.
Logic 1 = No interrupt pending. (default condition)
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source
Table 9
).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a log-
ic 1. ISR bit-4 indicates that the receiver detected a
data match of the Xon or Xoff character(s).
N
OTE
:
Note that once set to a logic 1, the ISR bit-4 will stay
a logic 1 until a Xon character is received. ISR bit-5 indi-
cates that CTS#/DSR# or RTS#/DTR# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are
disabled. They are set to a logic 1 when the FIFOs
are enabled.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
FCR BIT-0: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO. (de-
fault).
Logic 1 = Enable the transmit and receive FIFOs.
This bit must be set to logic 1 when other FCR bits
are written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive
FIFO
reset. (default)
Logic 1 = Reset the receive FIFO pointers and FIFO
level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset. (default)
P
RIORITY
ISR R
EGISTER
S
TATUS
B
ITS
S
OURCE
OF
THE
INTERRUPT
+
L
EVEL
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
1
2
3
4
5
6
7
X
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default)
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