參數(shù)資料
型號: XR16L788CQ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE OCTAL UART
中文描述: 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù): 16/42頁
文件大小: 557K
代理商: XR16L788CQ
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XR16L788 OCTAL UART
REV. 1.1.4
16
4.3
Each UART in the 788 includes the infrared encoder
and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The input pin ENIR conve-
niently activates all 8 UART channels to start up in
the infrared mode. This global control pin enables the
MCR bit-6 function in every UART channel register.
After power up or a reset, the software can overwrite
MCR bit-6 if so desired. ENIR and MCR bit-6 also dis-
able the receiver while the transmitter is sending da-
ta. This prevents echoed data from reaching the re-
ceiver. The global activation ENIR pin prevents the in-
frared emitter from turning on and drawing large
amount of current while the system is starting up.
When the infrared feature is enabled, the transmit da-
ta outputs, TX[7:0], would idle at logic zero level.
I
NFRARED
M
ODE
Likewise, the RX [7:0] inputs assume an idle level of
logic zero.
The infrared encoder sends out a
3/16 of a bit wide
HIGH-pulse for each “0” bit in the transmit data
stream. This signal encoding reduces the on-time of
the infrared LED, hence reduces the power consump-
tion. See
Figure 9
below.
The infrared decoder receives the input pulse from
the infrared sensing diode on RX pin. Each time it
senses a light pulse, it returns a logic zero to the data
bit stream. The decoder also accepts (when FCTR
bit-4 = 1) an inverted IR-encoded input signal. This
option supports active low instead of normal active
high pulse from some infrared modules on the mar-
ket.
4.4
Each UART channel provides an internal loopback
capability for system diagnostic purposes. The inter-
nal loopback mode
is enabled by setting MCR regis-
ter bit-4 to logic 1. All regular UART functions operate
normally.
Figure 10
shows how the modem port sig-
nals are re-configured. Transmit data from the trans-
I
NTERNAL
L
OOPBACK
mit shift register output is internally routed to the re-
ceive shift register input allowing the system to re-
ceive the same data that it was sending. The TX pin
is held at logic 1 or mark condition while RTS# and
DTR# are de-asserted, and CTS#, DSR# CD# and
RI# inputs are ignored.
F
IGURE
9. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
Character
Data Bits
S
S
0
0
0
0
0
1
1
1
1
1
Bit Time
1/16 Clock Delay
IRdecoder-1
RX Data
Receive
IR Pulse
(RX pin)
Character
Data Bits
S
S
0
0
0
0
0
1
1
1
1
1
TX Data
Transmit
IR Pulse
(TX Pin)
Bit Time
1/2 Bit Time
3/16 Bit Time
IrEncoder-1
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