參數(shù)資料
型號: XR16L788CQ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE OCTAL UART
中文描述: 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù): 22/42頁
文件大?。?/td> 557K
代理商: XR16L788CQ
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XR16L788 OCTAL UART
REV. 1.1.4
22
4.8.3
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR)
register and also encoded in INT (INT0-INT3) register
in the Device Configuration Registers.
Interrupt Enable Register (IER)
4.9
IER
VERSUS
R
ECEIVE
FIFO I
NTERRUPT
M
ODE
O
PERATION
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the RHR interrupts (see ISR bits 3 and 4) status will
reflect the following:
A.
The receive data available interrupts are issued
to the host when the FIFO has reached the pro-
F
IGURE
13. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X Clock
(8XMODE Register)
Receive Data Characters
Data Bit
Validation
Error
Flags in
LSR bits
4:2
F
IGURE
14. R
ECEIVER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Sampling
Clock (8XMODE Reg.)
E
(
E
L
64 bytes by 11-
bit wide FIFO
Receive Data Characters
FIFO Trigger=48
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Data fills to 56
Data falls to 40
Data Bit
Validation
Receive Data
FIFO
(64-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# re-asserts when data falls below
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
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