
XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. P1.2.0
á
PRELIMINARY
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
A
PPLICATIONS
........................................................................................................................................... 1
F
EATURES
................................................................................................................................................. 1
Figure 1. Block Diagram ....................................................................................................................... 1
Figure 2. Pin Out Assignment .............................................................................................................. 2
ORDERING
INFORMATION
............................................................................................................................ 2
PIN DESCRIPTIONS ....................................................................................................... 3
1.0 DESCRIPTION ........................................................................................................................................ 6
2.0 Functional Descriptions ........................................................................................................................ 6
2.1 D
EVICE
R
ESET
.............................................................................................................................................................. 6
2.1.1 Hardware Reset ....................................................................................................................... 6
2.1.2 Software Reset ......................................................................................................................... 6
2.2 UART C
HANNEL
S
ELECTION
......................................................................................................................................... 6
2.3 S
IMULTANEOUS
W
RITE
TO
A
LL
C
HANNELS
..................................................................................................................... 6
T
ABLE
1: UART C
HANNEL
S
ELECTION
...................................................................................................... 6
2.4 INT# O
UPUT
................................................................................................................................................................ 7
2.5 CRYSTAL OSCILLATOR / BUFFER .......................................................................................................................... 7
T
ABLE
2: INT# P
IN
O
PERATION
FOR
T
RANSMITTER
................................................................................... 7
T
ABLE
3: INT# P
IN
O
PERATION
F
OR
R
ECEIVER
......................................................................................... 7
Figure 3. Typical oscillator connections ............................................................................................. 7
2.6 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
.................................................................................................................... 8
Figure 4. External Clock Connection for Extended Data Rate .......................................................... 8
Figure 5. Baud Rate Generator ............................................................................................................. 8
2.7 T
RANSMITTER
............................................................................................................................................................... 9
2.7.1 Transmit Holding Register (THR) - Write Only ......................................................................... 9
2.7.2 Transmitter Operation in non-FIFO Mode ................................................................................ 9
T
ABLE
4: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
... 9
2.7.3 Transmitter Operation in FIFO Mode ..................................................................................... 10
2.8 R
ECEIVER
................................................................................................................................................................... 10
Figure 6. Transmitter Operation in non-FIFO Mode ......................................................................... 10
Figure 7. Transmitter Operation in FIFO and Flow Control Mode ................................................... 10
2.8.1 Receive Holding Register (RHR) - Read-Only ....................................................................... 11
Figure 8. Receiver Operation in non-FIFO Mode .............................................................................. 11
Figure 9. Receiver Operation in FIFO and Auto RTS Flow Control Mode ...................................... 11
2.9 THR
AND
RHR R
EGISTER
L
OCATIONS
........................................................................................................................ 12
2.10 A
UTOMATIC
RTS/DTR H
ARDWARE
F
LOW
C
ONTROL
O
PERATION
................................................................................ 12
T
ABLE
5: T
RANSMIT
AND
R
ECEIVE
D
ATA
R
EGISTER
, 16C550
COMPATIBLE
.............................................. 12
2.10.1 Auto CTS/DSR Flow Control ................................................................................................ 13
Figure 10. Auto RTS/DTR and CTS/DSR Flow Control Operation ................................................... 13
2.11 A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
......................................................................................................... 14
2.12 S
PECIAL
C
HARACTER
D
ETECT
.................................................................................................................................. 14
T
ABLE
6: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
........................................................................ 14
2.13 A
UTO
RS485 H
ALF
-
DUPLEX
C
ONTROL
..................................................................................................................... 15
2.14 I
NFRARED
M
ODE
....................................................................................................................................................... 15
Figure 11. Infrared Transmit Data Encoding and Receive Data Decoding ..................................... 16
2.15 S
LEEP
M
ODE
WITH
A
UTO
W
AKE
-U
P
......................................................................................................................... 17
2.16 I
NTERNAL
L
OOPBACK
................................................................................................................................................ 18
Figure 12. Internal Loop Back ............................................................................................................ 18
3.0 XR16L784 REGISTERS ........................................................................................................................ 19
3.1
DEVICE CONFIGURATION REGISTER SET ........................................................................................ 19
Figure 13. The XR16L784 Registers Mapping ................................................................................... 19
T
ABLE
7: XR16L784 R
EGISTER
S
ETS
..................................................................................................... 19
T
ABLE
8: D
EVICE
C
ONFIGURATION
R
EGISTERS
........................................................................................ 20