參數(shù)資料
型號: XR16L784IV
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
中文描述: 4 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁數(shù): 22/52頁
文件大?。?/td> 625K
代理商: XR16L784IV
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
á
REV. 1.2.0
22
3.1.2
General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (
DEFAULT
0
X
XX-XX-00-00)
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for a periodic event. An interrupt may be generated in the INT Register when the timer times out.
It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
T
ABLE
9: UART C
HANNEL
[3:0] I
NTERRUPT
S
OURCE
E
NCODING
AND
C
LEARING
P
RIORITY
B
IT
2 B
IT
1 B
IT
0
I
NTERRUPT
S
OURCE
(
S
)
AND
C
LEARING
x
0
0
0
None
1
0
0
1
RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the
RX FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR
register.
2
0
1
0
RXRDY Time-out: Cleared when the FIFO becomes empty.
3
0
1
1
TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
4
1
0
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
clear after reading MSR register; Xoff/Xon or special char. detect INT clears after reading
ISR register.
5
1
0
1
Reserved.
6
1
1
0
Reserved.
7
1
1
1
TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL regis-
ter. Reserved in other channels.
F
IGURE
15. T
IMER
/C
OUNTER
CIRCUIT
.
T
ABLE
10: TIMER CONTROL R
EGISTER
TIMERCNTL [0]
Logic 0 (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNLT [1]
Logic 0 (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2]
Logic0 (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3]
Logic 0 (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [7:4]
Reserved (defaults to zero).
TMRCK
OSC. CLOCK
TIMERCNTL [3]
16-Bit
Timer/Counter
TIMERCNTL [2]
Re-trigger
Single-shot
TIMERCNTL [1]
Start/Stop
TIMERCNTL [0]
Timer Interrupt, Ch-0 INT=7
No Interrupt
Time-out
Timer Interrupt Enable
Single/Re-triggerable
TIMERMSB and TIMERLSB
(16-bit Value)
0
1
0
1
0
1
Clock
Select
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