參數(shù)資料
型號： XR16L784IV-F
廠商： Exar Corporation
文件頁數(shù)： 21/51頁
文件大小： 0K
描述： IC UART 8B 3.3V QUAD 64LQFP
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
其它名稱： 1016-1282
XR16L784
28
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
REV. 1.2.3
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This interrupt is associated with bit-5 in the LSR register. An interrupt is issued whenever the THR becomes
empty or when data in the TX FIFO falls below the programmed trigger level.
Logic 0 = Disable Transmit Holding Register empty interrupt (default).
Logic 1 = Enable Transmit Holding Register empty interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bits 1-4 generate an interrupt immediately when
the character has been received.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition.
4.4
Interrupt Status Register (ISR) - Read Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table, Table 13, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16L784IVTR-F 功能描述:UART 接口集成電路 PCI BUS QUAD UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L788 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE OCTAL UART
XR16L788_05 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
XR16L788_08 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
XR16L788CQ 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
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